Skip to main content
SpringerLink
Log in

An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network

  • Research Paper
  • Published:
Science China Information Sciences Aims and scope Submit manuscript

Abstract

An accurate and highly-efficient analysis approach is crucial for a designer to evaluate the performance of on-chip networks. To this end, the novel M/G/1/N queuing models that capture various blocking phenomenon of the wormhole switching router are presented to compute the average waiting time accurately. With the M/G/1/N queuing models, this paper then presents the performance analysis algorithm to estimate some key metrics in terms of packet latency, buffer utilization, etc. The comparisons with SystemC simulated results show that the proposed approach with mean errors of 6.9% and 7.8% achieves the speedups of 117 and 101 for single-channel and multi-channel routers respectively. In our design methodology, this approach can direct NoC synthesis process effectively and then can be applied to multi-objective optimizations conveniently to find the best mappings.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Dally W J. Route packets, not wires: on-chip interconnection networks. In: Proceedings of Conference on Design Automation Conference (DAC’01), Las Vegas, 2001. 683–689

  2. Bjerregaard T, Mahadevan S. A survey of research and practices of network-on-chip. ACM Comput Surv, 2006, 38: 1–50

    Article  Google Scholar 

  3. Marculescu R, Ogras U Y, Li-Shiuan P, et al. Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives. IEEE Trans Comput Aid D, 2009, 28: 3–21

    Article  Google Scholar 

  4. Dally W J. Performance analysis of k-ary n-cube interconnection networks. IEEE Trans Comput, 1990, 39: 775–785

    Article  Google Scholar 

  5. Adve V S, Vernon M K. Performance analysis of mesh interconnection networks with deterministic routing. IEEE Trans Parall Distr, 1994, 5: 225–246

    Article  Google Scholar 

  6. Alzeidi N, Ould-Khaoua M, Khonsari A. A new general method to compute virtual channels occupancy probabilities in wormhole networks. J Comput Syst Sci, 2008, 74: 1033–1042

    Article  MathSciNet  MATH  Google Scholar 

  7. Hu J C, Ogras U Y, Marculescu R. System-level buffer allocation for application-specific networks-on-chip router design. IEEE Trans Comput Aid D, 2006, 25: 2919–2933

    Article  Google Scholar 

  8. Ogras U Y, Marculescu R. Analytical router modeling for networks-on-chip performance analysis. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE’ 07), Pittsburgh, 2007. 1096–1101

  9. Bogdan P, Marculescu R. Statistical physics approaches for network-on-chip traffic characterization. In: Proceedings of IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis, New York, 2009. 461–470

  10. Bogdan P, Marculescu R. Quantum-like effects in network-on-chip buffers behavior. In: Proceedings of Annual Design Automation Conference, New York, 2007. 266–267

  11. Huang T C, Ogras U Y, Marculescu R. Virtual channels planning for networks-on-chip. In: Proceedings of International Symposium on Quality Electronic Design, San Jose, 2007. 879–884

    Google Scholar 

  12. Ost L, Moraes F G, Maatta S. A simplified executable model to evaluate latency and throughput of networks-on-chip. In: Proceedings of Annual Symposium on Integrated Circuits and Systems Design, Brazil, 2008. 170–175

    Google Scholar 

  13. Ascia G, Catania V, Palesi M. Multi-objective mapping for mesh-based NoC architectures In: Proceedings of International Conference on Hardware/Software Codesign and System Synthesis, Sweden, 2004. 182–187

    Google Scholar 

  14. Tang L, Kumar S. A two-step genetic algorithm for mapping task graphs to a network on chip architecture. In: Proceedings of Euro-micro Symposium on Digital System Design, Turkey, 2003. 180–187

    Google Scholar 

  15. Guz Z, Walter I, Bolotin E, et al. Efficient link capacity and QoS design for wormhole network-on-chip. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE’ 06), Germany, 2006. 1–6

  16. Agarwal A. Limits on interconnection network. IEEE Trans Parall Distr, 1991, 2: 398–412

    Article  Google Scholar 

  17. Lu C L. Queuing Theory. Beijing: University of Posts and Telecommunications Press, 1994

    Google Scholar 

  18. Gelenbe E, Pujolle G. Introduction to Queuing Network. 2nd ed. New York: John Wiley and Sons, 1987. 121–135

    Google Scholar 

  19. Medhi J. Stochastic Models in Queuing Theory. Amsterdam/Boston: Elsevier Academic Press, 2002. 234–238

    Google Scholar 

  20. Hassan M, Sarker R, Atiquzzaman M. Modeling IP-ATM gateway using M/G/1/N queue. In: Proceedings of Conference on IEEE Global Telecommunications, Sydney, 1998. 465–470

    Google Scholar 

  21. Frey A, Takahashi Y. A note on an M/G/1/N queue with vacation time and exhaustive service discipline. Oper Res Lett, 1997, 21: 95–100

    Article  MathSciNet  MATH  Google Scholar 

  22. Karol M J, Hluchyj M G, Morgan S P. Input versus output queuing on a space-division packet switch. IEEE Trans Commun, 1987, 35: 1347–1356

    Article  Google Scholar 

  23. Kachigan S. Statistical Analysis. New York: Radius Press, 1986

    Google Scholar 

  24. Matsutani H, Koibuchi M, Amano H, et al. Prediction router: yet another low latency on-chip router architecture. In: Proceedings of IEEE International Symposium on High Performance Computer Architecture (HPCA’ 09), North Carolina, 2009. 367–378

  25. Lai M C, Gao L, Ma S et al. A practical low-latency router architecture with wing channel for on-chip network Microprocess Microsy, 2011, 35: 98–109

    Article  Google Scholar 

  26. Chrysostomos A, Park D, Kim J, et al. ViChaR: a dynamic virtual channel regulator for network-on-chip routers. In: Proceedings of Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’ 06), Florida, 2006. 134–146

    Google Scholar 

  27. Chen X N, Peh L-S. Leakage power modeling and optimization in interconnection networks. In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED’ 03), Seoul, 2003. 90–95

  28. Hsu C H, Chen H Y, Chang Y W. Multi-layer global routing considering via and wire capacities. In: Proceedings of the International Conference on Computer Aided Design (ICCAD’ 09), San Jose, 2008. 250–355

  29. Vangal S, Howard J, Ruhl G, et al. An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS. In: Proceedings of Conference on Solid-State Circuits, San Francisco, 2007. 98–100

  30. Chi H C. Design and implementation of a routing switch for on-chip interconnection networks. In: Proceedings of Asia-Pacific Conference on Advanced System Integrated Circuits, Tokyo, 2004. 392–395

  31. Rajeev S, Stunkel C B, Panda D K. HIPIQS: a high-performance switch architecture using input queuing. IEEE Trans Parall Distr, 2002, 13: 275–289

    Article  Google Scholar 

  32. Hu J C, Marculescu R. Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans Comput Aid D, 2005, 24: 551–562

    Article  Google Scholar 

  33. Deb K, Pratap A, Agarwal S, et al. A fast and elitist multi-objective genetic algorithm: NSGA-II. IEEE Trans Evolut Comput, 2002, 6: 182–197

    Article  Google Scholar 

  34. de Mello A V, Moraes F G. Evaluation of Routing Algorithms on Mesh Based NOCS. Tech Rep. Brazil: Faculdade de Informatica PUCRS, 2004

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer, National University of Defense Technology, Changsha, 410073, China

    MingChe Lai, Lei Gao, Nong Xiao & ZhiYing Wang

Authors
  1. MingChe Lai
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Lei Gao
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Nong Xiao
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. ZhiYing Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to MingChe Lai.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Lai, M., Gao, L., Xiao, N. et al. An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network. Sci. China Inf. Sci. 56, 1–20 (2013). https://doi.org/10.1007/s11432-012-4648-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11432-012-4648-x

Keywords

Search

Navigation