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A novel ESD power supply clamp circuit with double pull-down paths

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Abstract

Electrostatic-discharge (ESD) protection design is one of the key challenges of advanced CMOS processes. RC-triggered and MOSFET-based power supply ESD clamp circuits have been widely used to obtain the desired ESD protection ability. In this paper, a MOSFET-based ESD power clamp circuit with only 10 ns RC time constant for 0.18-μm process is presented. A double pull-down path is proposed to avoid false triggering, reject power supply noise and reduce energy consumption. The performance of the novel clamp circuit is excellent, consuming very small layout area. The simulation results show that this clamp circuit can be used in industry.

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Authors and Affiliations

  1. Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi’an, 710071, China

    HongXia Liu, ZhaoNian Yang, Li Li & QingQing Zhuo

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  1. HongXia Liu
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  2. ZhaoNian Yang
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  3. Li Li
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  4. QingQing Zhuo
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Correspondence to HongXia Liu.

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Liu, H., Yang, Z., Li, L. et al. A novel ESD power supply clamp circuit with double pull-down paths. Sci. China Inf. Sci. 56, 1–8 (2013). https://doi.org/10.1007/s11432-012-4699-z

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  • DOI: https://doi.org/10.1007/s11432-012-4699-z

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