Abstract
This paper proposes a VLSI architecture of the optimized Speeded-Up Robust Feature (SURF) algorithm. The SURF algorithm which is widely used in computer vision applications, locates interest points (IPoints) and extracts feature descriptors based on the surrounding gradients. In the proposed approach, the SURF algorithm is modified to make it more suitable for hardware implementation with little accuracy lost compared to OpenSURF, an open source software implementation based on OpenCV. The resource cost and throughput gain are balanced. Word Length Reduction (WLR) is adopted to compress the integral image and reduce the occupied memory resources. The orientations and the feature descriptors of the IPoints are calculated in a more efficient way, which significantly reduces memory accesses. Moreover, the operations are pipelined both in and among the proposed hardware modules. This VLSI architecture has been validated on FPGA (Xilinx Virtex-4 XC4VLX80), which is able to detect IPoints and extract SURF feature descriptors in a VGA (640 × 480) 64 fps video input with a 96 MHz working frequency while dissipating 1.278 W. This throughput is more than double of the ones reported in the latest literatures.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Bay H, Ess A, Tuytelaars T, et al. SURF: Speeded up robust features. Computer Vis Image Underst, 2008, 110: 346–359
Lowe D. Object recognition from local scale-invariant features. In: Proceedings of the 7th IEEE International Conference on Computer Vision, Kerkyra, 1999. 1150–1157
Jungling K, Arens M. Feature based person detection beyond the visible spectrum. In: IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, Miami, 2009. 30–37
Zhu H, Zhao G, Wang J. Image based assistant localization in urban navigation. In: IEEE Intelligent Vehicles Symposium, Xi’an, 2009. 388–392
Wang A, Wang Z, Lv D, et al. Research on a novel non-rigid registration for medical image based on SURF and APSO. In: 3rd International Congress on Image and Signal Processing, Yantai, 2010. 2628–2633
Huang K, Tsai Y, Tsai C, et al. Video stabilization for vehicular applications using SURF-like descriptor and KD-tree. In: 17th IEEE International Conference on Image Processing, Hong Kong, 2010. 3517–3520
Luo J, Gwun O. SURF applied in panorama image stitching. In: 2nd International Conference on Image Processing Theory Tools and Applications, Paris, 2010. 495–499
Li B C, Shang K K, Zheng Y. Study on the mosaicing methods for microscopy image of blood cells based on speededup robust features. In: IEEE 3rd International Conference on Communication Software and Networks, Xi’an, 2011. 321–324
Besbes B, Apatean A, Rogozan A, et al. Combining SURF-based local and global features for road obstacle recognition in far infrared images. In: 13th International IEEE Conference on Intelligent Transportation Systems, Funchal, 2010. 1869–1874
Jang D M, Turk M. Car-Rec: A real time car recognition system. In: IEEE Workshop on Applications of Computer Vision, Kona, 2011. 599–605
Belt H. Word length reduction for the integral image. In: 15th IEEE International Conference on Image Processing, San Diego, 2008. 805–808
Han B, Wang Y, Jia X. Fast calculating feature point’s main orientation in SURF algorithm. In: International Conference on Computer, Mechatronics, Control and Electronic Engineering, Changchun, 2010. 165–168
Bonato V, Marques E, Constantinides G. A parallel hardware architecture for scale and rotation invariant feature detection. IEEE Trans Circuits Syst Video Technol, 2008, 18: 1703–1712
Yao L, Feng H, Zhu Y, et al. An architecture of optimised sift feature detection for an FPGA implementation of an image matcher. In: International Conference on Field-Programmable Technology, Sydney, 2009. 30–37
Kim J, Kim M, Lee S, et al. A 201.4 GOPS 496 mW real-time multi-object recognition processor with bio-inspired neural perception engine. IEEE J Solid-State Circuit, 2010, 45: 32–45
Svab J, Krajnik T, Faigl J, et al. FPGA based speeded up robust features. In: IEEE International Conference on Technologies for Practical Robot Applications, Woburn, 2009. 35–41
Bouris D, Nikitakis A, Papaefstathiou I. Fast and efficient FPGA-based feature detection employing the SURF algorithm. In: 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, Charlotte, 2010. 3–10
Schaeferling M, Kiefer G. Flex-SURF: A flexible architecture for FPGA-based robust feature extraction for optical tracking systems. International Conference on Reconfigurable Computing and FPGAs, Quintana Roo, 2010. 458–463
Evans C. Notes on the openSURF library. Technical Report CSTR-09-001, University of Bristol, 2009
Ke Y, Sukthankar R. PCA-SIFT: a more distinctive representation for local image descriptors. In: Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition, Washington DC, 2004. II-506–II-513
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Zhang, W., Liu, L., Yin, S. et al. An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video. Sci. China Inf. Sci. 56, 1–14 (2013). https://doi.org/10.1007/s11432-013-4786-9
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11432-013-4786-9