Abstract
With the aggressive scaling of device technology, the leakage power has become the main part of power consumption, which seriously reduces the energy recovery efficiency of adiabatic logic. In this paper, a novel low-power adiabatic logic based on FinFET devices has been proposed. Due to the lower leakage current, higher on-state current and design flexibility of FinFETs, the proposed adiabatic logic shows considerable power reduction, performance improvement and area saving compared with CMOS adiabatic logic. An 8-state clock chain as the test circuit has been demonstrated based on the 32-nm FinFET Predictive Technology Model. The simulation results show that adiabatic circuit based on FinFET devices achieves a power reduction of up to 84.8% and a limiting frequency of up to 55 GHz.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Synopsys Inc. CCS Power Technical White Paper. Version 3.0, 2006
Denker J S. A review of adiabatic computing. In: IEEE Symposium on Low Power Electronics, San Diego, 1994. 94–97
Calhoun B H, Khanna S, Mann R, et al. Sub-threshold circuit design with shrinking CMOS devices. In: IEEE International Symposium on Circuits and Systems, Taipei, 2009. 2541–2544
Hemantha S, Dhawan A, Haranath K. Multi-threshold CMOS design for low power digital circuits. In: 2008 IEEE Region 10 Conference on TENCON, Hyderabad, 2008. 1–5
Li L F, Hu J P, Yu L L. Low-power register file using N-type and P-type adiabatic logic circuits. In: Pacific-Asia Conference on Circuits, Communications and Systems, Chengdu, 2009. 342–345
Samson M, Mandavalli S. Adiabatic 5T SRAM. In: 2011 International Symposium on Electronic System Design, Kochi, 2011. 267–272
Chanda M, Dandapat A, Rahaman H. Low-power sequential circuit using single phase adiabatic dynamic logic. In: 2009 International Conference on Computers and Devices for Communication, Kolkata, 2009. 1–4
Bai X F, Huang L, Wang Y F, et al. Evaluation of DPA attack resistance of transistor-based adiabatic logic styles. In: 2nd International Conference on e-Business and Information System Security, Wuhan, 2010. 1–3
Monteiro C, Takahashi Y, Sekine T. Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card. In: International Symposium on Intelligent Signal Processing and Communications Systems, Chiang Mai, 2011. 1–5
Mukhopadhyay S, Raychowdhury A, Roy K. Accurate estimation of total leakage in nanometer-scale bulk CMOS circuit based on device geometry and doping profile. IEEE Trans Comput Aid Des Integr Circuit Syst, 2005, 24: 363–381
Hisamoto D, Lee W C, Kedzierski J, et al. FinFETA self-aligned double gate MOSFET scalable to 20 nm. IEEE Trans Electron Dev, 2000, 47: 2320–2325
Thakker R A, Sathe C, Sachid A B, et al. A novel table-based approach for design of FinFET circuits. IEEE Trans Comput Aid Des Integr Circuit Syst, 2009, 28: 1061–1070
Endo K, O’uchi S I, Ishikawa Y, et al. Independent-double-gate FinFET SRAM for leakage current reduction. IEEE electron dev lett, 2009, 30: 757–759
Hsieh C Y, Fan M L, Hu V P H, et al. Independently-controlled-gate FinFET Schmitt trigger sub-threshold SRAMs. IEEE Trans Very Large Scale Integr Syst, 2012, 20: 1201–1210
Jafari F, Mosaffa M, Mohammadi S. Designing robust asynchronous circuits based on FinFET technology. In: 2011 14th Euromicro Conference on Digital System Design, Oulu, 2011. 401–408
Rasouli S H, Koike H, Banerjee K. High-speed low-power FinFET based domino logic. In: Asia and South Pacific Design Automation Conference, Yokohama, 2009. 829–834
Mishra P, Muttreja A, Jha, N K. Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis. In: IEEE International Symposium on Nanoscale Architectures, Anaheim, 2008. 77–84
Kramer A, Denker J S, Flower B, et al. 2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits. In: Proceedings of the 1995 International Symposium on Low Power Design. New York: ACM, 1995. 191–196
Varga L, Kovacs F, Hosszu G. An improved pass-gate adiabatic logic. In: 14th Annual IEEE International ASIC/SOC Conference, Arlington, 2001. 208–211
Blotti A, Saletti R. Ultralow-power adiabatic circuit semi-custom design. IEEE Trans Very Large Scale Integr Syst, 2011, 12: 1248–1253
Bhaaskaran V S K. Energy recovery performance of quasi-adiabatic circuits using lower technology nodes. In: 2010 India International Conference on Power Electronics, New Delhi, 2011. 1–7
Zhao W, Cao Y. Predictive technology model for nano-CMOS design exploration. ACM J Emerg Technol Comput Syst, 2007, 3: 1
Moon Y, Jeong D K. An efficient charge recovery logic circuit. IEEE J Solid-State Circuits, 1996, 31: 514–522
Trivedi V P, Fossum J G, Zhang W M. Threshold voltage and bulk inversion effects in nonclassical CMOS devices with undoped ultra-thin bodies. Solid-State Electron, 2007, 1: 170–178
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Liao, N., Cui, X., Liao, K. et al. Low power adiabatic logic based on FinFETs. Sci. China Inf. Sci. 57, 1–13 (2014). https://doi.org/10.1007/s11432-013-4902-x
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11432-013-4902-x