Abstract
This paper presents a design for a low-power, high-resolution audio ΣΔ analog-to-digital converter (ADC) based on a novel gain-boost class-C inverter. The gain-boost class-C inverter behaves as a sub-threshold amplifier, thereby minimizing power dissipation. The proposed ADC chip is fabricated in a SMIC 65-nm CMOS process with a die area of 0.63 mm2. With 1.2 V of supply voltage, the ADC chip achieves a peak signal-to-noise-plus-distortion-ratio (SNDR) of 92 dB and a dynamic range (DR) of 97 dB over the 20 kHz audio band, consuming only 1.13 mW. These results make the ADC particularly suitable for portable electronics applications.
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Liu, X., Han, Y., Han, X. et al. A low-power inverter-based ΣΔ analog-to-digital converter for audio applications. Sci. China Inf. Sci. 57, 1–10 (2014). https://doi.org/10.1007/s11432-013-4999-y
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DOI: https://doi.org/10.1007/s11432-013-4999-y