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Polar-coded forward error correction for MLC NAND flash memory

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Abstract

With the ever-growing storage density, high-speed, and low-cost data access, flash memory has inevitably become popular. Multi-level cell (MLC) NAND flash memory, which can well balance the data density and memory stability, has occupied the largest market share of flash memory. With the aggressive memory scaling, however, the reliability decays sharply owing to multiple interferences. Therefore, the control system should be embedded with a suitable error correction code (ECC) to guarantee the data integrity and accuracy. We proposed the pre-check scheme which is a multi-strategy polar code scheme to strike a balance between reasonable frame error rate (FER) and decoding latency. Three decoders namely binary-input, quantized-soft, and pure-soft decoders are embedded in this scheme. Since the calculation of soft log-likelihood ratio (LLR) inputs needs multiple sensing operations and optional quantization boundaries, a 2-bit quantized hard-decision decoder is proposed to outperform the hard-decoded LDPC bit-flipping decoder with fewer sensing operations. We notice that polar codes have much lower computational complexity compared with LDPC codes. The stepwise maximum mutual information (SMMI) scheme is also proposed to obtain overlapped boundaries without exhausting search. The mapping scheme using Gray code is employed and proved to achieve better raw error performance compared with other alternatives. Hardware architectures are also given in this paper.

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References

  1. Li S, Zhang T. Improving multi-level NAND flash memory storage reliability using concatenated BCH-TCM coding. IEEE Trans VLSI Syst, 2010, 18: 1412–1420

    Google Scholar 

  2. Kim J, Sung W. Low-energy error correction of NAND flash memory through soft-decision decoding. EURASIP J Adv Signal Process, 2012, 2012: 195

    Article  Google Scholar 

  3. Grupp L M, Davis J D, Swanson S. The bleak future of NAND flash memory. In: Proceedings of the 10th USENIX Conference on File and Storage Technologies, San Jose, 2012

    Google Scholar 

  4. Bellorado J, Yaakobi E. Signal processing and coding for non-volatile memories. Non-Volatile Memory Workshop, 2013. https://doi.org/faculty.cs.tamu.edu/ajiang/NVMWTutorial.pdf

    Google Scholar 

  5. Li Y, Lee S, Fong Y, et al. A 16 Gb 3-Bit per cell (X3) NAND flash memory on 56 nm technology with 8 MB/s write rate. IEEE J Solid-State Circ, 2009, 44: 195–207

    Article  Google Scholar 

  6. Shibata N, Maejima H, Isobe K, et al. A 70 nm 16 Gb 16-level-cell NAND flash memory. IEEE J Solid-State Circ, 2008, 43: 929–937

    Article  Google Scholar 

  7. Trinh C, Shibata N, Nakano T, et al. A 5.6 MB/s 64 Gb 4b/cell NAND flash memory in 43 nm CMOS. In: Proceedings of IEEE International Solid-State Circuits Conference, San Francisco, 2009. 246–247

    Google Scholar 

  8. Ho K C, Chen C L, Liao Y C, et al. A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. In: Proceedings of IEEE International Symposiuim on Circuits and Systems, Lisbon, 2015. 1450–1453

    Google Scholar 

  9. Dong G Q, Xie N D, Zhang T. On the use of soft-decision error-correction codes in NAND flash memory. IEEE Trans Circ Syst I, 2011, 58: 429–439

    MathSciNet  Google Scholar 

  10. Kim J, Lee D, Sung W. Performance of rate 0.96 (68254, 65536) EG-LDPC code for NAND flash memory error correction. In: Proceedings of IEEE International Conference on Communications, Ottawa, 2012. 7029–7033

    Google Scholar 

  11. Cui Z Q, Wang Z F, Huang X M. Multilevel error correction scheme for MLC flash memory. In: Proceedings of IEEE International Symposium on Circuits and Systems, Melbourne, 2014. 201–204

    Google Scholar 

  12. Chen B N, Zhang X M, Wang Z F. Error correction for multi-level NAND flash memory using Reed-Solomon codes. In: Proceedings of IEEE Workshop on Signal Processing Systems, Washington, 2008. 94–99

    Google Scholar 

  13. Xu Q Y, Pan Z W, Liu N, et al. A complexity-reduced fast successive cancellation list decoder for polar codes. Sci China Inf Sci, 2018, 61: 022309

    Article  MathSciNet  Google Scholar 

  14. Chen Z, Yin L G, Pei Y K, et al. CodeHop: physical layer error correction and encryption with LDPC-based code hopping. Sci China Inf Sci, 2016, 59: 102309

    Article  Google Scholar 

  15. Zhang C, Parhi K K. A network-efficient nonbinary QC-LDPC decoder architecture. IEEE Trans Circ Syst I, 2012, 59: 1359–1371

    MathSciNet  Google Scholar 

  16. Zhang C, Wang Z F, Sha J, et al. Flexible LDPC decoder design for multigigabit-per-second applications. IEEE Trans Circ Syst I, 2010, 57: 116–124

    MathSciNet  Google Scholar 

  17. Arıkan E. Channel polarization: a method for constructing capacity-achieving codes for symmetric binary-input memoryless channels. IEEE Trans Inf Theory, 2009, 55: 3051–3073

    Article  MathSciNet  MATH  Google Scholar 

  18. Zhang C, Yuan B, Parhi K K. Reduced-latency sc polar decoder architectures. In: Proceedings of IEEE International Conference on Communications, Ottawa, 2012. 3471–3475

    Google Scholar 

  19. Zhang C, Parhi K K. Low-latency sequential and overlapped architectures for successive cancellation polar decoder. IEEE Trans Signal Process, 2013, 61: 2429–2441

    Article  MathSciNet  MATH  Google Scholar 

  20. Zhang C, Parhi K K. Latency analysis and architecture design of simplified SC polar decoders. IEEE Trans Circ Syst II, 2014, 61: 115–119

    Google Scholar 

  21. Zhang C, You X, Sha J. Hardware architecture for list successive cancellation polar decoder. In: Proceedings of IEEE International Symposium on Circuits and Systems, Melbourne, 2014. 209–212

    Google Scholar 

  22. Zhang C, Yang J, You X, et al. Pipelined implementations of polar encoder and feed-back part for SC polar decoder. In: Proceedings of IEEE International Symposiuim on Circuits and Systems, Lisbon, 2015. 3032–3035

    Google Scholar 

  23. AccelerComm. BLER performance of list decoding for enhanced turbo codes. 3GPP TSG RAN WG1 Meeting #87, 2016. https://eprints.soton.ac.uk/404002/1/R1-1612308.pdf

    Google Scholar 

  24. Li Y, Alhussien H, Haratsch E, et al. A study of polar codes for MLC NAND flash memories. In: Proceedings of International Conference on Computing, Networking and Communications, Garden Grove, 2015. 608–612

    Google Scholar 

  25. Atwood G, Fazio A, Mills D, et al. Intel strataflash memory technology overview. Intel Technol J, 1997, 4: 1–8

    Google Scholar 

  26. Cai Y, Haratsch E F, Mutlu O, et al. Error patterns in MLC NAND flash memory: measurement, characterization, and analysis. In: Proceedings of the Conference on Design, Automation and Test in Europe, Dresden, 2012. 521–526

    Google Scholar 

  27. Leroux C, Tal I, Vardy A, et al. Hardware architectures for successive cancellation decoding of polar codes. In: Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing, Czech, 2011. 1665–1668

    Book  Google Scholar 

  28. Song H C, Zhang C, Zhang S Q, et al. Polar code-based error correction code scheme for NAND flash memory applications. In: Proceedings of International Conference onWireless Communications and Signal Processing, Yangzhou, 2016

    Book  Google Scholar 

  29. Wang J D, Courtade T, Shankar H, et al. Soft information for LDPC decoding in flash: mutual-information optimized quantization. In: Proceedings of IEEE Global Telecommunications Conference, Kathmandu, 2011

    Google Scholar 

  30. Wang J D, Dong G Q, Zhang T, et al. Mutual-information optimized quantization for LDPC decoding of accurately modeled flash data. 2012. ArXiv:1202.1325

    Google Scholar 

  31. Mielke N, Marquart T, Wu N, et al. Bit error rate in NAND flash memories. In: Proceedings of IEEE International Reliability Physics Symposium, Phoenix, 2008. 9–19

    Google Scholar 

  32. Takeuchi K. Novel co-design of NAND flash memory and NAND flash controller circuits for sub-30 nm low-power high-speed solid-state drives (SSD). IEEE J Solid-State Circ, 2009, 44: 1227–1234

    Article  Google Scholar 

  33. Blankenship Y, Kuffner S. LDPC decoding for 802.22 standard. IEEE P802.22, 2007

    Google Scholar 

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Acknowledgements

This work was supported in part by National Natural Science Foundation of China (NSFC) (Grant Nos. 61501116, 61571105), Jiangsu Provincial NSF for Excellent Young Scholars (Grant No. BK20140636), Huawei HIRP Flagship (Grant No. YB201504), Fundamental Research Funds for the Central Universities, SRTP of Southeast University, State Key Laboratory of ASIC & System (Grant No. 2016KF007), ICRI for MNC, and Project Sponsored by the SRF for the Returned Overseas Chinese Scholars of MoE.

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Authors and Affiliations

  1. Lab of Efficient Architectures for Digital-communication and Signal-processing (LEADS), National Mobile Communications Research Laboratory, Southeast University, Nanjing, 211189, China

    Haochuan Song & Chuan Zhang

  2. Quantum Information Center of Southeast University, Nanjing, 211189, China

    Haochuan Song, Zaichen Zhang & Chuan Zhang

  3. National Mobile Communications Research Laboratory, Southeast University, Nanjing, 211189, China

    Haochuan Song, Zaichen Zhang, Xiaohu You & Chuan Zhang

  4. Lite-On Technology Corporation, Guangzhou, 510000, China

    Jen-Chien Fu & Shih-Jia Zeng

  5. School of Electronic Science and Engineering, Nanjing University, Nanjing, 210046, China

    Jin Sha

Authors
  1. Haochuan Song
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  2. Jen-Chien Fu
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  3. Shih-Jia Zeng
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  4. Jin Sha
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  5. Zaichen Zhang
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  6. Xiaohu You
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  7. Chuan Zhang
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Correspondence to Chuan Zhang.

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Song, H., Fu, JC., Zeng, SJ. et al. Polar-coded forward error correction for MLC NAND flash memory. Sci. China Inf. Sci. 61, 102307 (2018). https://doi.org/10.1007/s11432-017-9394-y

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  • DOI: https://doi.org/10.1007/s11432-017-9394-y

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