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Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing

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Abstract

Crossbar architecture has been considered as an efficient means to execute a matrix-vector multiplication computation. An efficient evaluation model for this computation including the interconnect resistance effect on the high density resistive random access memmory (RRAM) crossbar array is proposed in this paper. The proposed model considers the interconnect resistance impacts on the columns and rows separately. The simulation results indicate that the computing speed of the proposed model can be boosted by over three orders of magnitude with the computation deviation of 7.7% in comparison with the precise comprehensive model in the 64 kb crossbar array fabricated at the 14 nm technology node. Based on the proposed evaluation model, the impacts of the parameters including nonlinearity and load resistance, on the computation are discussed along with solutions to improve the computational performance.

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References

  1. Wong H S P, Lee H Y, Yu S, et al. Metal-oxide RRAM. Proc IEEE, 2012, 100: 1951–1970

    Article  Google Scholar 

  2. Hudec B, Hsu C W, Wang I T, et al. 3D resistive RAM cell design for high-density storage class memory-a review. Sci China Inf Sci, 2016, 59: 061403

    Article  Google Scholar 

  3. Waser R, Dittmann R, Staikov G, et al. Redox-based resistive switching memories: nanoionic mechanisms, prospects, and challenges. Adv Mater, 2009, 21: 2632–2663

    Article  Google Scholar 

  4. Borghetti J, Snider G S, Kuekes P J, et al. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature, 2010, 464: 873–876

    Article  Google Scholar 

  5. Yang J J, Strukov D B, Stewart D R. Memristive devices for computing. Nat Nanotech, 2013, 8: 13–24

    Article  Google Scholar 

  6. Huang P, Kang J F, Zhao Y D, et al. Reconfigurable nonvolatile logic operations in resistance switching crossbar array for large-scale circuits. Adv Mater, 2016, 28: 9758–9764

    Article  Google Scholar 

  7. Hu M, Li H, Chen Y R, et al. Memristor crossbar-based neuromorphic computing system: a case study. IEEE Trans Neural Netw Learn Syst, 2014, 25: 1864–1878

    Article  Google Scholar 

  8. Upadhyay N K, Joshi S, Yang J J. Synaptic electronics and neuromorphic computing. Sci China Inf Sci, 2016, 59: 061404

    Article  Google Scholar 

  9. Cao J D, Li R X. Fixed-time synchronization of delayed memristor-based recurrent neural networks. Sci China Inf Sci, 2017, 60: 032201

    Article  Google Scholar 

  10. Yu S M, Gao B, Fang Z, et al. A low energy oxide-based electronic synaptic device for neuromorphic visual systems with tolerance to device variation. Adv Mater, 2013, 25: 1774–1779

    Article  Google Scholar 

  11. Hu M, Li H, Wu Q, et al. Hardware realization of BSB recall function using memristor crossbar arrays. In: Proceedings of the 49th Annual Design Automation Conference, San Francisco, 2012. 498–503

    Google Scholar 

  12. Gu P, Li B X, Tang T Q, et al. Technological exploration of RRAM crossbar array for matrix-vector multiplication. In: Proceedings of the 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, 2015. 106–111

    Google Scholar 

  13. Gao L G, Chen P Y, Yu S M. Demonstration of convolution kernel operation on resistive cross-point array. IEEE Electron Device Lett, 2016, 37: 870–873

    Article  Google Scholar 

  14. Li H T, Gao B, Chen Z, et al. A learnable parallel processing architecture towards unity of memory and computing. Sci Rep, 2015, 5: 013330

    Article  Google Scholar 

  15. Semiconductor Industry Association. International Technology Roadmap for Semiconductors. 2015. https://www. semiconductors.org/main/2015 international technology roadmap for semiconductors itrs/

  16. Chen A. A comprehensive crossbar array model with solutions for line resistance and nonlinear device characteristics. IEEE Trans Electron Device, 2013, 60: 1318–1326

    Article  Google Scholar 

  17. Vontobel P O, Robinett W, Kuekes P J, et al. Writing to and reading from a nano-scale crossbar memory based on memristors. Nanotechnology, 2009, 20: 425204

    Article  Google Scholar 

  18. Deng Y X, Huang P, Chen B, et al. RRAM crossbar array with cell selection device: a device and circuit interaction study. IEEE Trans Electron Device, 2013, 60: 719–726

    Article  Google Scholar 

  19. Huang P, Liu X Y, Chen B, et al. A physics-based compact model of metal-oxide-based RRAM DC and AC operations. IEEE Trans Electron Device, 2013, 60: 4090–4097

    Article  Google Scholar 

  20. Sheridan P M, Cai F X, Du C, et al. Sparse coding with memristor networks. Nat Nanotech, 2017, 12: 784–789

    Article  Google Scholar 

  21. Li C, Hu M, Li Y N, et al. Analogue signal and image processing with large memristor crossbars. Nat Electron, 2018, 1: 52–59

    Article  Google Scholar 

Download references

Acknowledgements

This work was supported by National Natural Science Foundation of China (Grant Nos. 61334007, 61421005), and Shenzhen Science and Technology Innovation Committee (Grant No. JCYJ2017041215-0411676).

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Authors and Affiliations

  1. Institute of Microelectronics, Peking University, Beijing, 100871, China

    Runze Han, Peng Huang, Yudi Zhao, Xiaoyan Liu & Jinfeng Kang

  2. Key Lab of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen, 518055, China

    Xiaole Cui

Authors
  1. Runze Han
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  2. Peng Huang
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  3. Yudi Zhao
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  4. Xiaole Cui
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  5. Xiaoyan Liu
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  6. Jinfeng Kang
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Corresponding authors

Correspondence to Xiaole Cui or Jinfeng Kang.

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Han, R., Huang, P., Zhao, Y. et al. Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing. Sci. China Inf. Sci. 62, 22401 (2019). https://doi.org/10.1007/s11432-018-9555-8

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  • DOI: https://doi.org/10.1007/s11432-018-9555-8

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