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Acknowledgements
This work was supported in part by National Key Research and Development Plan (Grant No. 2016YFA0200504), National Science and Technology Major Project (Grant No. 2017ZX02315001-004), Program of National Natural Science Foundation of China (Grant Nos. 61421005, 61774012, 61574010), Beijing Innovation Center for Future Chips Foundation (Grant No. KYJJ2016008), and the 111 Project (Grant No. B18001).
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Dong, X., Li, M., Zhang, W. et al. Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors. Sci. China Inf. Sci. 63, 209402 (2020). https://doi.org/10.1007/s11432-019-2658-x
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DOI: https://doi.org/10.1007/s11432-019-2658-x