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Experimental investigation of the gate voltage range of negative differential capacitance in ferroelectric transistors

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Conclusion

In this study, the impacts of sweeping rate and device parameters on the gate voltage range of the NDC phenomenon are investigated based on experiments. With the increase of the frequency and dielectric capacitance, the beginning gate voltage of the NC emergence will increase, and the gate duration voltage range and the maximum gate voltage amplification factor appear to increase first and then decrease. This work suggests a big challenge for scaled NCFETs to operate at high frequency with low VDD.

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References

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Acknowledgements

This work was supported by National Key R&D Program of China (Grant No. 2018YFB2202801), National Natural Science Foundation of China (Grant Nos. 61822401, 61851401, 61927901, 61421005), and 111 Project (Grant No. B18001).

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Authors and Affiliations

  1. Key Laboratory of Microelectronic Devices and Circuits (MOE), Institute of Microelectronics, Peking University, Beijing, 100871, China

    Mengxuan Yang, Qianqian Huang, Chang Su, Liang Chen, Yangyuan Wang & Ru Huang

  2. Beijing Laboratory of Future IC Technology and Science, Peking University, Beijing, 100871, China

    Qianqian Huang, Yangyuan Wang & Ru Huang

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  1. Mengxuan Yang
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  2. Qianqian Huang
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  3. Chang Su
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  4. Liang Chen
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  5. Yangyuan Wang
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  6. Ru Huang
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Corresponding authors

Correspondence to Qianqian Huang or Ru Huang.

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Yang, M., Huang, Q., Su, C. et al. Experimental investigation of the gate voltage range of negative differential capacitance in ferroelectric transistors. Sci. China Inf. Sci. 65, 169402 (2022). https://doi.org/10.1007/s11432-021-3268-0

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  • DOI: https://doi.org/10.1007/s11432-021-3268-0

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