Skip to main content
Log in

In-memory computing with emerging nonvolatile memory devices

  • Review
  • Published:
Science China Information Sciences Aims and scope Submit manuscript

Abstract

The von Neumann bottleneck and memory wall have posed fundamental limitations in latency and energy consumption of modern computers based on von Neumann architecture. In-memory computing represents a radical shift in the computer architecture that can address such problems by merging computing functions within the memory itself. In this article, we review the emerging nonvolatile memory devices, such as resistance-based and charge-based memory devices, that are explored for in-memory computing applications. We will provide an overview of the materials, mechanisms, and integration of these devices, and discuss the optimizations at the device and array levels that are required to better support in-memory computing. Recent progress in the application of in-memory computing in artificial neural networks, spiking neural networks, digital logic in memory as well as hardware security will also be discussed. Finally, we will discuss the remaining challenges in this field and potential pathways to address them.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. Wulf W A, McKee S A. Hitting the memory wall: implications of the obvious. ACM SIGARCH Comput Archit News, 1995, 23: 20–24

    Article  Google Scholar 

  2. Horowitz M. Computing’s energy problem (and what we can do about it). In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2014. 10–14

  3. Backus J. Can programming be liberated from the von Neumann style? Commun ACM, 1978, 21: 613–641

    Article  MATH  Google Scholar 

  4. Merolla P A, Arthur J V, Alvarez-Icaza R, et al. A million spiking-neuron integrated circuit with a scalable communication network and interface. Science, 2014, 345: 668–673

    Article  Google Scholar 

  5. Waldrop M M. The chips are down for Moore’s law. Nature, 2016, 530: 144–147

    Article  Google Scholar 

  6. Mutlu O, Ghose S, Gómez-Luna J, et al. Processing data where it makes sense: enabling in-memory computation. Microprocessors MicroSyst, 2019, 67: 28–41

    Article  Google Scholar 

  7. Alpern B, Carter L, Feig E, et al. The uniform memory hierarchy model of computation. Algorithmica, 1994, 12: 72–109

    Article  MATH  Google Scholar 

  8. Balasubramonian R, Albonesi D, Buyuktosunoglu A, et al. Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. In: Proceedings of IEEE/ACM International Symposium on Microarchitecture, 2000. 245–257

  9. Keckler S W, Dally W J, Khailany B, et al. GPUs and the future of parallel computing. IEEE Micro, 2011, 31: 7–17

    Article  Google Scholar 

  10. Jouppi N P, Young C, Patil N, et al. In-datacenter performance analysis of a tensor processing unit. In: Proceedings of ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017. 1–12

  11. Sze V, Chen Y H, Yang T J, et al. Efficient processing of deep neural networks: a tutorial and survey. Proc IEEE, 2017, 105: 2295–2329

    Article  Google Scholar 

  12. Patterson D, Anderson T, Cardwell N, et al. A case for intelligent RAM. IEEE Micro, 1997, 17: 34–44

    Article  Google Scholar 

  13. Ahn J, Yoo S, Mutlu O, et al. PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture. In: Proceedings of ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), 2015. 336–348

  14. Sebastian A, Le Gallo M, Khaddam-Aljameh R, et al. Memory devices and applications for in-memory computing. Nat Nanotech, 2020, 15: 529–544

    Article  Google Scholar 

  15. Ielmini D, Wong H S P. In-memory computing with resistive switching devices. Nat Electron, 2018, 1: 333–343

    Article  Google Scholar 

  16. Wong H S P, Salahuddin S. Memory leads the way to better computing. Nat Nanotech, 2015, 10: 191–194

    Article  Google Scholar 

  17. Zhu J, Zhang T, Yang Y, et al. A comprehensive review on emerging artificial neuromorphic devices. Appl Phys Rev, 2020, 7: 011312

    Article  Google Scholar 

  18. Ma W, Zidan M A, Lu W D. Neuromorphic computing with memristive devices. Sci China Inf Sci, 2018, 61: 060422

    Article  Google Scholar 

  19. Li Y, Zhou Y X, Wang Z R, et al. Memcomputing: fusion of memory and computing. Sci China Inf Sci, 2018, 61: 060424

    Article  Google Scholar 

  20. Haario H, Laine M, Mira A, et al. DRAM: efficient adaptive MCMC. Stat Comput, 2006, 16: 339–354

    Article  Google Scholar 

  21. Jacob B, Ng S, Wang D. Memory Systems: Cache, DRAM, Disk. San Francisco: Morgan Kaufmann, 2010

    Google Scholar 

  22. Chung Y, Song S H. Implementation of low-voltage static RAM with enhanced data stability and circuit speed. MicroElectron J, 2009, 40: 944–951

    Article  Google Scholar 

  23. Lanza M, Wong H S P, Pop E, et al. Recommended methods to study resistive switching devices. Adv Electron Mater, 2019, 5: 1800143

    Article  Google Scholar 

  24. Raoux S, Burr G W, Breitwisch M J, et al. Phase-change random access memory: a scalable technology. IBM J Res Dev, 2008, 52: 465–479

    Article  Google Scholar 

  25. Scott J F, de Araujo C A P. Ferroelectric memories. Science, 1989, 246: 1400–1405

    Article  Google Scholar 

  26. Bez R, Camerlenghi E, Modelli A, et al. Introduction to flash memory. Proc IEEE, 2003, 91: 489–502

    Article  Google Scholar 

  27. Goldhaber-Gordon D, Montemerlo M S, Love J C, et al. Overview of nanoelectronic devices. Proc IEEE, 1997, 85: 521–540

    Article  Google Scholar 

  28. Chen A, Hutchby J, Zhirnov V, et al. Emerging Nanoelectronic Devices. Hoboken: John Wiley & Sons, 2014

    Book  Google Scholar 

  29. Chua L. Memristor-the missing circuit element. IEEE Trans Circuit Theor, 1971, 18: 507–519

    Article  Google Scholar 

  30. Chua L. Resistance switching memories are memristors. In: Handbook of Memristor Networks. Cham: Springer, 2019. 197–230

    Chapter  Google Scholar 

  31. Wang Z, Joshi S, Savel’ev S E, et al. Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing. Nat Mater, 2017, 16: 101–108

    Article  Google Scholar 

  32. Jo S H, Chang T, Ebong I, et al. Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett, 2010, 10: 1297–1301

    Article  Google Scholar 

  33. Ravichandran V, Li C, Banagozar A, et al. Artificial neural networks based on memristive devices. Sci China Inf Sci, 2018, 61: 060423

    Article  Google Scholar 

  34. Yang C J, Adhikari S P, Kim H. Excitatory and inhibitory actions of a memristor bridge synapse. Sci China Inf Sci, 2018, 61: 060427

    Article  Google Scholar 

  35. Tang J, Yuan F, Shen X, et al. Bridging biological and artificial neural networks with emerging neuromorphic devices: fundamentals, progress, and challenges. Adv Mater, 2019, 31: 1902761

    Article  Google Scholar 

  36. Kumar S, Graves C E, Strachan J P, et al. Direct observation of localized radial oxygen migration in functioning tantalum oxide memristors. Adv Mater, 2016, 28: 2772–2776

    Article  Google Scholar 

  37. Kumar S, Wang Z, Huang X, et al. Conduction channel formation and dissolution due to oxygen thermophoresis/diffusion in hafnium oxide memristors. ACS Nano, 2016, 10: 11205–11210

    Article  Google Scholar 

  38. Wuttig M, Yamada N. Phase-change materials for rewriteable data storage. Nat Mater, 2007, 6: 824–832

    Article  Google Scholar 

  39. Lencer D, Salinga M, Grabowski B, et al. A map for phase-change materials. Nat Mater, 2008, 7: 972–977

    Article  Google Scholar 

  40. Martin L W, Rappe A M. Thin-film ferroelectric materials and their applications. Nat Rev Mater, 2017, 2: 16087

    Article  Google Scholar 

  41. Kim S J, Mohan J, Summerfelt S R, et al. Ferroelectric Hf0.5Zr0.5O2 thin films: a review of recent advances. JOM, 2019, 71: 246–255

    Article  Google Scholar 

  42. Novoselov K S. Electric field effect in atomically thin carbon films. Science, 2004, 306: 666–669

    Article  Google Scholar 

  43. Dean C R, Young A F, Meric I, et al. Boron nitride substrates for high-quality graphene electronics. Nat Nanotech, 2010, 5: 722–726

    Article  Google Scholar 

  44. Stuart M A C, Huck W T S, Genzer J, et al. Emerging applications of stimuli-responsive polymer materials. Nat Mater, 2010, 9: 101–113

    Article  Google Scholar 

  45. Laoutid F, Bonnaud L, Alexandre M, et al. New prospects in flame retardant polymer materials: from fundamentals to nanocomposites. Mater Sci Eng-R-Rep, 2009, 63: 100–125

    Article  Google Scholar 

  46. Pan F, Gao S, Chen C, et al. Recent progress in resistive random access memories: materials, switching mechanisms, and performance. Mater Sci Eng-R-Rep, 2014, 83: 1–59

    Article  Google Scholar 

  47. Lee S R, Kim Y B, Chang M, et al. Multi-level switching of triple-layered TaOx RRAM with excellent reliability for storage class memory. In: Proceedings of Symposium on VLSI Technology (VLSIT), 2012. 71–72

  48. Li J, Yang Y, Yin M, et al. Electrochemical and thermodynamic processes of metal nanoclusters enabled biorealistic synapses and leaky-integrate-and-fire neurons. Mater Horiz, 2020, 7: 71–81

    Article  Google Scholar 

  49. Dan Y, Poo M. Spike timing-dependent plasticity of neural circuits. Neuron, 2004, 44: 23–30

    Article  Google Scholar 

  50. van Rossum M C W, Bi G Q, Turrigiano G G. Stable Hebbian learning from spike timing-dependent plasticity. J Neurosci, 2000, 20: 8812–8821

    Article  Google Scholar 

  51. Caporale N, Dan Y. Spike timing-dependent plasticity: a Hebbian learning rule. Annu Rev Neurosci, 2008, 31: 25–46

    Article  Google Scholar 

  52. Lu Y, Liu K, Yang J, et al. Highly uniform two-terminal artificial synapses based on polycrystalline Hf0.5Zr0.5O2 for sparsified back propagation networks. Adv Electron Mater, 2020, 6: 2000204

    Article  Google Scholar 

  53. Cheng C, Li Y, Zhang T, et al. Bipolar to unipolar mode transition and imitation of metaplasticity in oxide based memristors with enhanced ionic conductivity. J Appl Phys, 2018, 124: 152103

    Article  Google Scholar 

  54. Abraham W C. Metaplasticity: tuning synapses and networks for plasticity. Nat Rev Neurosci, 2008, 9: 387

    Article  Google Scholar 

  55. Tan Z H, Yang R, Terabe K, et al. Synaptic metaplasticity realized in oxide memristive devices. Adv Mater, 2016, 28: 377–384

    Article  Google Scholar 

  56. Hao Y, Xiang S Y, Han G, et al. Recent progress of integrated circuits and optoelectronic chips. Sci China Inf Sci, 2021, 64: 201401

    Article  Google Scholar 

  57. Tan H, Liu G, Zhu X, et al. An optoelectronic resistive switching memory with integrated demodulating and arithmetic functions. Adv Mater, 2015, 27: 2797–2803

    Article  Google Scholar 

  58. Ye C, Peng Q, Li M, et al. Multilevel conductance switching of memory device through photoelectric effect. J Am Chem Soc, 2012, 134: 20053–20059

    Article  Google Scholar 

  59. Dang B, Ma L, Yan L, et al. Physically transient optic-neural synapse for secure in-sensor computing. IEEE Electron Device Lett, 2020, 41: 1641–1644

    Article  Google Scholar 

  60. Srikant V, Clarke D R. On the optical band gap of zinc oxide. J Appl Phys, 1998, 83: 5447–5451

    Article  Google Scholar 

  61. Seo S, Jo S H, Kim S, et al. Artificial optic-neural synapse for colored and color-mixed pattern recognition. Nat Commun, 2018, 9: 5106

    Article  Google Scholar 

  62. Yang Y, Yin M, Yu Z, et al. Multifunctional nanoionic devices enabling simultaneous heterosynaptic plasticity and efficient in-memory boolean logic. Adv Electron Mater, 2017, 3: 1700032

    Article  Google Scholar 

  63. Lai S, Lowrey T. OUM-A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications. In: Proceedings of International Electron Devices Meeting, 2001. 1–4

  64. Rao F, Ding K, Zhou Y, et al. Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing. Science, 2017, 358: 1423–1427

    Article  Google Scholar 

  65. Im D H, Lee J I, Cho S L, et al. A unified 7.5 nm dash-type confined cell for high performance PRAM device. In: Proceedings of IEEE International Electron Devices Meeting, 2008. 1–4

  66. Kolobov A V, Fons P, Frenkel A I, et al. Understanding the phase-change mechanism of rewritable optical media. Nat Mater, 2004, 3: 703–708

    Article  Google Scholar 

  67. Khwa W S, Wu J Y, Su T H, et al. A novel inspection and annealing procedure to rejuvenate phase change memory from cycling-induced degradations for storage class memory applications. In: Proceedings of IEEE International Electron Devices Meeting, 2014. 1–4

  68. Song Z T, Cai D L, Li X, et al. High endurance phase change memory chip implemented based on carbon-doped Ge2Sb2Te5 in 40 nm node for embedded application. In: Proceedings of IEEE International Electron Devices Meeting, 2018. 1–4

  69. Lu Y M, Li X, Yan L H, et al. Accelerated local training of CNNs by optimized direct feedback alignment based on stochasticity of 4 Mb C-doped Ge2Sb2Te5 PCM chip in 40 nm node. In: Proceedings of IEEE International Electron Devices Meeting, 2020. 1–4

  70. Garcia V, Fusil S, Bouzehouane K, et al. Giant tunnel electroresistance for non-destructive readout of ferroelectric states. Nature, 2009, 460: 81–84

    Article  Google Scholar 

  71. Pantel D, Goetze S, Hesse D, et al. Room-temperature ferroelectric resistive switching in ultrathin Pb(Zr0.2Ti0.8)O3 films. ACS Nano, 2011, 5: 6032–6038

    Article  Google Scholar 

  72. Li Z, Guo X, Lu H B, et al. An epitaxial ferroelectric tunnel junction on silicon. Adv Mater, 2014, 26: 7185–7189

    Article  Google Scholar 

  73. Chang P Y, Du G, Liu X Y. Design space for stabilized negative capacitance in HfO2 ferroelectric-dielectric stacks based on phase field simulation. Sci China Inf Sci, 2021, 64: 122402

    Article  Google Scholar 

  74. Park M H, Lee Y H, Kim H J, et al. Ferroelectricity and antiferroelectricity of doped thin HfO2-based films. Adv Mater, 2015, 27: 1811–1831

    Article  Google Scholar 

  75. Yoong H Y, Wu H, Zhao J, et al. Epitaxial ferroelectric Hf0.5Zr0.5O2 thin films and their implementations in memristors for brain-inspired computing. Adv Funct Mater, 2018, 28: 1806037

    Article  Google Scholar 

  76. Mikheev V, Chouprik A, Lebedinskii Y, et al. Memristor with a ferroelectric HfO2 layer: in which case it is a ferroelectric tunnel junction. Nanotechnology, 2020, 31: 215205

    Article  Google Scholar 

  77. Chen C, Yang M, Liu S, et al. Bio-inspired neurons based on novel leaky-FeFET with ultra-low hardware cost and advanced functionality for all-ferroelectric neural network. In: Proceedings of Symposium on VLSI Technology, 2019. 136–137

  78. Pirrotta O, Larcher L, Lanza M, et al. Leakage current through the poly-crystalline HfO2: trap densities at grains and grain boundaries. J Appl Phys, 2013, 114: 134503

    Article  Google Scholar 

  79. Luo Q, Cheng Y, Yang J, et al. A highly CMOS compatible hafnia-based ferroelectric diode. Nat Commun, 2020, 11: 1391

    Article  Google Scholar 

  80. Seo J, Brezzo B, Liu Y, et al. A 45 nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. In: Proceedings of IEEE Custom Integrated Circuits Conference (CICC), 2011. 1–4

  81. Indiveri G, Linares-Barranco B, Hamilton T J, et al. Neuromorphic silicon neuron circuits. Front Neurosci, 2011, 5: 73

    Article  Google Scholar 

  82. Liu Y H, Wang X J. Spike-frequency adaptation of a generalized leaky integrate-and-fire model neuron. J Comput Neuroscience, 2001, 10: 25–45

    Article  Google Scholar 

  83. Andrade R, Foehring R C, Tzingounis A V. The calcium-activated slow AHP: cutting through the Gordian knot. Front Cell Neurosci, 2012, 6: 47

    Article  Google Scholar 

  84. Sharpee T O, Sugihara H, Kurgansky A V, et al. Adaptive filtering enhances information transmission in visual cortex. Nature, 2006, 439: 936–942

    Article  Google Scholar 

  85. Luo J, Yu L, Liu T, et al. Capacitor-less stochastic leaky-FeFET neuron of both excitatory and inhibitory connections for SNN with reduced hardware cost. In: Proceedings of IEEE International Electron Devices Meeting, 2019. 1–4

  86. Ali T, Polakowski P, Riedel S, et al. High endurance ferroelectric hafnium oxide-based FeFET memory without retention penalty. IEEE Trans Electron Devices, 2018, 65: 3769–3774

    Article  Google Scholar 

  87. Garcia H, Dueñas S, Castán H, et al. Influence of interlayer trapping and detrapping mechanisms on the electrical characterization of hafnium oxide/silicon nitride stacks on silicon. J Appl Phys, 2008, 104: 094107

    Article  Google Scholar 

  88. Ali T, Polakowski P, Kähnel K, et al. A multilevel FeFET memory device based on laminated HSO and HZO ferroelectric layers for high-density storage. In: Proceedings of IEEE International Electron Devices Meeting, 2019. 1–4

  89. Muller J, Polakowski P, Paul J, et al. Integration challenges of ferroelectric hafnium oxide based embedded memory. ECS Trans, 2015, 69: 85–95

    Article  Google Scholar 

  90. Sarkar D, Xie X, Liu W, et al. A subthermionic tunnel field-effect transistor with an atomically thin channel. Nature, 2015, 526: 91–95

    Article  Google Scholar 

  91. Wang Q H, Kalantar-Zadeh K, Kis A, et al. Electronics and optoelectronics of two-dimensional transition metal dichalcogenides. Nat Nanotech, 2012, 7: 699–712

    Article  Google Scholar 

  92. Das S, Robinson J A, Dubey M, et al. Beyond graphene: progress in novel two-dimensional materials and van der Waals solids. Annu Rev Mater Res, 2015, 45: 1–27

    Article  Google Scholar 

  93. Yang H, Xiao M, Cui Y, et al. Nonvolatile memristor based on heterostructure of 2D room-temperature ferroelectric α-In2 Se3 and WSe2. Sci China Inf Sci, 2019, 62: 220404

    Article  Google Scholar 

  94. Tian H, Guo Q, Xie Y, et al. Anisotropic black phosphorus synaptic device for neuromorphic applications. Adv Mater, 2016, 28: 4991–4997

    Article  Google Scholar 

  95. Xia F, Wang H, Jia Y. Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics. Nat Commun, 2014, 5: 4458

    Article  Google Scholar 

  96. Schulman D S, Arnold A J, Das S. Contact engineering for 2D materials and devices. Chem Soc Rev, 2018, 47: 3037–3058

    Article  Google Scholar 

  97. Zhu J, Yang Y, Jia R, et al. Ion gated synaptic transistors based on 2D van der Waals crystals with tunable diffusive dynamics. Adv Mater, 2018, 30: 1800195

    Article  Google Scholar 

  98. Upadhyayula L C, Loferski J J, Wold A, et al. Semiconducting properties of single crystals of n- and p-type tungsten diselenide (WSe2). J Appl Phys, 1968, 39: 4736–4740

    Article  Google Scholar 

  99. Kuzminskii Y V, Voronin B M, Redin N N. Iron and nickel phosphorus trisulfides as electroactive materials for primary lithium batteries. J Power Sources, 1995, 55: 133–141

    Article  Google Scholar 

  100. Barj M, Sourisseau C, Ouvrard G, et al. Infrared studies of lithium intercalation in the FePS3 and NiPS3 layer-type compounds. Solid State Ion, 1983, 11: 179–183

    Article  Google Scholar 

  101. Bao L, Zhu J, Yu Z, et al. Dual-gated MoS2 neuristor for neuromorphic computing. ACS Appl Mater Interfaces, 2019, 11: 41482–41489

    Article  Google Scholar 

  102. Pan L, Ji Z, Yi X, et al. Metal-organic framework nanofilm for mechanically flexible information storage applications. Adv Funct Mater, 2015, 25: 2677–2685

    Article  Google Scholar 

  103. Fang Y K, Liu C L, Li C, et al. Synthesis, morphology, and properties of poly(3-hexylthiophene)-block-poly(vinylphenyl oxadiazole) donor-acceptor rod-coil block copolymers and their memory device applications. Adv Funct Mater, 2010, 20: 3012–3024

    Article  Google Scholar 

  104. Ji Y, Cho B, Song S, et al. Stable switching characteristics of organic nonvolatile memory on a bent flexible substrate. Adv Mater, 2010, 22: 3071–3075

    Article  Google Scholar 

  105. Hsu J M, Rieth L, Normann R A, et al. Encapsulation of an integrated neural interface device with Parylene C. IEEE Trans Biome Eng, 2008, 56: 23–29

    Article  Google Scholar 

  106. Kahouli A, Sylvestre A, Ortega L, et al. Structural and dielectric study of parylene C thin films. Appl Phys Lett, 2009, 94: 152901

    Article  Google Scholar 

  107. Cai Y, Tan J, YeFan L, et al. A flexible organic resistance memory device for wearable biomedical applications. Nanotechnology, 2016, 27: 275206

    Article  Google Scholar 

  108. Lin M, Chen Q, Wang Z, et al. Flexible polymer device based on parylene-C with memory and temperature sensing functionalities. Polymers, 2017, 9: 310

    Article  Google Scholar 

  109. Zhang Z, Wang Z, Shi T, et al. Memory materials and devices: from concept to application. InfoMat, 2020, 2: 261–290

    Article  Google Scholar 

  110. Schönhals A, Rosário C M M, Hoffmann-Eifert S, et al. Role of the electrode material on the RESET limitation in oxide ReRAM devices. Adv Electron Mater, 2018, 4: 1700243

    Article  Google Scholar 

  111. Valov I, Waser R, Jameson J R, et al. Electrochemical metallization memories-fundamentals, applications, prospects. Nanotechnology, 2011, 22: 254003

    Article  Google Scholar 

  112. Lim E W, Ismail R. Conduction mechanism of valence change resistive switching memory: a survey. Electronics, 2015, 4: 586–613

    Article  Google Scholar 

  113. Moors M, Adepalli K K, Lu Q, et al. Resistive switching mechanisms on TaOx and SrRuO3 thin-film surfaces probed by scanning tunneling microscopy. ACS Nano, 2016, 10: 1481–1492

    Article  Google Scholar 

  114. Yang J J, Inoue I H, Mikolajick T, et al. Metal oxide memories based on thermochemical and valence change mechanisms. MRS Bull, 2012, 37: 131–137

    Article  Google Scholar 

  115. Yang J J, Pickett M D, Li X, et al. Memristive switching mechanism for metal/oxide/metal nanodevices. Nat Nanotech, 2008, 3: 429–433

    Article  Google Scholar 

  116. Ielmini D. Resistive switching memories based on metal oxides: mechanisms, reliability and scaling. Semicond Sci Technol, 2016, 31: 063002

    Article  Google Scholar 

  117. Akinaga H, Shima H. Resistive random access memory (ReRAM) based on metal oxides. Proc IEEE, 2010, 98: 2237–2251

    Article  Google Scholar 

  118. Lee J, Lu W D. On-demand reconfiguration of nanomaterials: when electronics meets ionics. Adv Mater, 2018, 30: 1702770

    Article  Google Scholar 

  119. Grundmeier G, Schmidt W, Stratmann M. Corrosion protection by organic coatings: electrochemical mechanism and novel methods of investigation. Electrochim Acta, 2000, 45: 2515–2533

    Article  Google Scholar 

  120. Liu Q, Long S, Lv H, et al. Controllable growth of nanoscale conductive filaments in solid-electrolyte-based ReRAM by using a metal nanocrystal covered bottom electrode. ACS Nano, 2010, 4: 6162–6168

    Article  Google Scholar 

  121. Yang Y, Gao P, Li L, et al. Electrochemical dynamics of nanoscale metallic inclusions in dielectrics. Nat Commun, 2014, 5: 4232

    Article  Google Scholar 

  122. Yang Y, Zhang X, Qin L, et al. Probing nanoscale oxygen ion motion in memristive systems. Nat Commun, 2017, 8: 1–10

    Google Scholar 

  123. Liu K, Qin L, Zhang X, et al. Interfacial redox processes in memristive devices based on valence change and electrochemical metallization. Faraday Discuss, 2019, 213: 41–52

    Article  Google Scholar 

  124. Kwon D H, Kim K M, Jang J H, et al. Atomic structure of conducting nanofilaments in TiO2 resistive switching memory. Nat Nanotech, 2010, 5: 148–153

    Article  Google Scholar 

  125. Valov I, Linn E, Tappertzhofen S, et al. Nanobatteries in redox-based resistive switches require extension of memristor theory. Nat Commun, 2013, 4: 1771

    Article  Google Scholar 

  126. Tappertzhofen S, Valov I, Tsuruoka T, et al. Generic relevance of counter charges for cation-based nanoscale resistive switching memories. ACS Nano, 2013, 7: 6396–6402

    Article  Google Scholar 

  127. Guan W, Long S, Liu Q, et al. Nonpolar nonvolatile resistive switching in Cu Doped ZrO2. IEEE Electron Device Lett, 2008, 29: 434–437

    Article  Google Scholar 

  128. Chae S C, Lee J S, Kim S, et al. Random circuit breaker network model for unipolar resistance switching. Adv Mater, 2008, 20: 1154–1159

    Article  Google Scholar 

  129. Strukov D B, Alibart F, Williams R S. Thermophoresis/diffusion as a plausible mechanism for unipolar resistive switching in metal-oxide-metal memristors. Appl Phys A, 2012, 107: 509–518

    Article  Google Scholar 

  130. Murgatroyd P N. Theory of space-charge-limited current enhanced by Frenkel effect. J Phys D-Appl Phys, 1970, 3: 151–156

    Article  Google Scholar 

  131. Liu Q, Liu Z, Zhang X, et al. Organic photovoltaic cells based on an acceptor of soluble graphene. Appl Phys Lett, 2008, 92: 223303

    Article  Google Scholar 

  132. Carbone A, Kotowska B K, Kotowski D. Space-charge-limited current fluctuations in organic semiconductors. Phys Rev Lett, 2005, 95: 236601

    Article  Google Scholar 

  133. Hill R M. Poole-Frenkel conduction in amorphous solids. Philos Mag, 1971, 23: 59–86

    Article  Google Scholar 

  134. Kim W, Park S I, Zhang Z, et al. Current conduction mechanism of nitrogen-doped AlOx RRAM. IEEE Trans Electron Dev, 2014, 61: 2158–2163

    Article  Google Scholar 

  135. Jeong D S, Hwang C S. Tunneling-assisted Poole-Frenkel conduction mechanism in HfO2 thin films. J Appl Phys, 2005, 98: 113701

    Article  Google Scholar 

  136. Chen Y C, Chen C F, Chen C T, et al. An access-transistor-free (0T/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device. In: Proceedings of IEEE International Electron Devices Meeting, 2003. 1–4

  137. Mazumder P, Kang S M, Waser R. Memristors: devices, models, and applications. Proc IEEE, 2012, 100: 1911–1919

    Article  Google Scholar 

  138. Jiang W, Xie B, Liu C C, et al. Integrating memristors and CMOS for better AI. Nat Electron, 2019, 2: 376–377

    Article  Google Scholar 

  139. Cai F, Correll J M, Lee S H, et al. A fully integrated reprogrammable memristor-CMOS system for efficient multiply-accumulate operations. Nat Electron, 2019, 2: 290–299

    Article  Google Scholar 

  140. Yang X, Fang Y, Yu Z, et al. Nonassociative learning implementation by a single memristor-based multi-terminal synaptic device. Nanoscale, 2016, 8: 18897–18904

    Article  Google Scholar 

  141. Scott J C. Is there an immortal memory? Science, 2004, 304: 62–63

    Article  Google Scholar 

  142. Baek I G, Kim D C, Lee M J, et al. Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application. In: Proceedings of IEEE International Electron Devices Meeting, 2005. 750–753

  143. Seok J Y, Song S J, Yoon J H, et al. A review of three-dimensional resistive switching cross-bar array memories from the integration and materials property points of view. Adv Funct Mater, 2014, 24: 5316–5339

    Article  Google Scholar 

  144. Hsu C W, Wang I T, Lo C L, et al. Self-rectifying bipolar TaOx/TiO2 RRAM with superior endurance over 1012 cycles for 3D high-density storage-class memory. In: Proceedings of Symposium on VLSI Technology, 2013. 166–167

  145. Bai Y, Wu H, Wang K, et al. Stacked 3D RRAM array with graphene/CNT as edge electrodes. Sci Rep, 2015, 5: 13785

    Article  Google Scholar 

  146. Yoon H S, Baek I G, Zhao J, et al. Vertical cross-point resistance change memory for ultra-high density non-volatile memory applications. In: Proceedings of Symposium on VLSI Technology, 2009. 26–27

  147. Deng Y, Chen H Y, Gao B, et al. Design and optimization methodology for 3D RRAM arrays. In: Proceedings of IEEE International Electron Devices Meeting, 2013. 1–4

  148. Yu M, Fang Y, Wang Z, et al. Encapsulation layer design and scalability in encapsulated vertical 3D RRAM. Nanotechnology, 2016, 27: 205202

    Article  Google Scholar 

  149. Lee S M, Cahill D G. Heat transport in thin dielectric films. J Appl Phys, 1997, 81: 2590–2595

    Article  Google Scholar 

  150. Chen Y S, Lee H Y, Chen P S, et al. Good endurance and memory window for Ti/HfOx pillar RRAM at 50-nm scale by optimal encapsulation layer. IEEE Electron Device Lett, 2011, 32: 390–392

    Article  Google Scholar 

  151. Chen Q, Wang Z, Yu M, et al. Thermal effect in ultra-high density 3D vertical and horizontal RRAM array. Phys Scr, 2019, 94: 045001

    Article  Google Scholar 

  152. Li S, Niu D, Malladi K T, et al. Drisa: a DRAM-based reconfigurable in-situ accelerator. In: Proceedings of the 50th Annual IEEE/ACM International Symposium Microarchit (MICRO), 2017. 288–301

  153. Seshadri V, Lee D, Mullins T, et al. Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology. In: Proceedings of the 50th Annual IEEE/ACM International Symposium Microarchit (MICRO), 2017. 273–287

  154. Yin S, Jiang Z, Seo J S, et al. XNOR-SRAM: in-memory computing SRAM Macro for binary/ternary deep neural networks. IEEE J Solid-State Circ, 2020, 55: 1733–1743

    Google Scholar 

  155. Irom F, Nguyen D N. Single event effect characterization of high density commercial NAND and NOR nonvolatile flash memories. IEEE Trans Nucl Sci, 2007, 54: 2547–2553

    Article  Google Scholar 

  156. Xiang Y, Huang P, Han R, et al. Hardware implementation of energy efficient deep learning neural network based on nanoscale flash computing array. Adv Mater Technol, 2019, 4: 1800720

    Article  Google Scholar 

  157. Chiu F C. A review on conduction mechanisms in dielectric films. Adv Mater Sci Eng, 2014, 2014: 1–18

    Google Scholar 

  158. Cheong W, Yoon C, Woo S, et al. A flash memory controller for 15 µs ultra-low-latency SSD using high-speed 3D NAND flash with 3 µs read time. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2018. 338–340

  159. Miura N, Take Y, Saito M, et al. A 2.7 Gb/s/mm2 0.9 pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2011. 490–492

  160. Guo X, Bayat F M, Bavandpour M, et al. Fast, energy-efficient, robust, and reproducible mixed-signal neuromorphic classifier based on embedded NOR flash memory technology. In: Proceedings of IEEE International Electron Devices Meeting, 2017. 1–4

  161. Bayat F M, Guo X, Klachko M, et al. Model-based high-precision tuning of NOR flash memory cells for analog computing applications. In: Proceedings of the 74th Annual Device Research Conference (DRC), 2016. 1–2

  162. Mahmoodi M R, Strukov D. An ultra-low energy internally analog, externally digital vector-matrix multiplier based on NOR flash memory technology. In: Proceedings of the 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 2018. 1–6

  163. Han R, Huang P, Xiang Y, et al. A novel convolution computing paradigm based on NOR flash array with high computing speed and energy efficiency. IEEE Trans Circ Syst I, 2019, 66: 1692–1703

    Google Scholar 

  164. Lee S T, Lee J H. Neuromorphic computing using NAND flash memory architecture with pulse width modulation scheme. Front Neurosci, 2020, 14: 571292

    Article  Google Scholar 

  165. Govoreanu B, Kar G S, Chen Y Y, et al. 10 × 10 nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation. In: Proceedings of IEEE International Electron Devices Meeting, 2011. 1–4

  166. Torrezan A C, Strachan J P, Medeiros-Ribeiro G, et al. Sub-nanosecond switching of a tantalum oxide memristor. Nanotechnology, 2011, 22: 485203

    Article  Google Scholar 

  167. Xiong F, Liao A D, Estrada D, et al. Low-power switching of phase-change materials with carbon nanotube electrodes. Science, 2011, 332: 568–570

    Article  Google Scholar 

  168. Florent K, Pesic M, Subirats A, et al. Vertical ferroelectric HfO2 FET based on 3-D NAND architecture: towards dense low-power memory. In: Proceedings of IEEE International Electron Devices Meeting, 2018. 1–4

  169. Dünkel S, Trentzsch M, Richter R, et al. A FeFET based super-low-power ultra-fast embedded NVM technology for 22 nm FDSOI and beyond. In: Proceedings of IEEE International Electron Devices Meeting, 2017. 1–4

  170. Zhang F, Zhang H, Shrestha P R, et al. An ultra-fast multi-level MoTe2-based RRAM. In: Proceedings of IEEE International Electron Devices Meeting, 2018. 1–4

  171. Xu W, Min S Y, Hwang H, et al. Organic core-sheath nanowire artificial synapses with femtojoule energy consumption. Sci Adv, 2016, 2: e1501326

    Article  Google Scholar 

  172. Huang R, Cai Y, Liu Y, et al. Resistive switching in organic memory devices for flexible applications. In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2014. 838–841

  173. Yan B N, Chen Y R, Li H. Challenges of memristor based neuromorphic computing system. Sci China Inf Sci, 2018, 61: 060425

    Article  Google Scholar 

  174. Zhou Y, Wu H, Gao B, et al. Associative memory for image recovery with a high-performance memristor array. Adv Funct Mater, 2019, 29: 1900155

    Article  Google Scholar 

  175. Gao B, Chen B, Zhang F, et al. A novel defect-engineering-based implementation for high-performance multilevel data storage in resistive switching memory. IEEE Trans Electron Dev, 2013, 60: 1379–1383

    Article  Google Scholar 

  176. Kim W, Menzel S, Wouters D J, et al. 3-bit multilevel switching by deep reset phenomenon in Pt/W/TaOX/Pt-ReRAM devices. IEEE Electron Device Lett, 2016, 37: 564–567

    Article  Google Scholar 

  177. Li J, Duan Q, Zhang T, et al. Tuning analog resistive switching and plasticity in bilayer transition metal oxide based memristive synapses. RSC Adv, 2017, 7: 43132–43140

    Article  Google Scholar 

  178. Ren P, Wang R, Ji Z, et al. New insights into the design for end-of-life variability of NBTI in scaled high-κ/metal-gate technology for the nano-reliability era. In: Proceedings of IEEE International Electron Devices Meeting, 2014. 1–4

  179. Fang Y, Yu Z, Wang Z, et al. Improvement of HfOx-based RRAM device variation by inserting ALD TiN buffer layer. IEEE Electron Device Lett, 2018, 39: 819–822

    Article  Google Scholar 

  180. Kim S, Choi S H, Lu W. Comprehensive physical model of dynamic resistive switching in an oxide memristor. ACS Nano, 2014, 8: 2369–2376

    Article  Google Scholar 

  181. Bi G, Poo M. Synaptic modifications in cultured hippocampal neurons: dependence on spike timing, synaptic strength, and postsynaptic cell type. J Neurosci, 1998, 18: 10464–10472

    Article  Google Scholar 

  182. Wang Z, Yin M, Zhang T, et al. Engineering incremental resistive switching in TaOx based memristors for brain-inspired computing. Nanoscale, 2016, 8: 14015–14022

    Article  Google Scholar 

  183. Kannan S, Rajendran J, Karri R, et al. Sneak-path testing of crossbar-based nonvolatile random access memories. IEEE Trans Nanotechnol, 2013, 12: 413–426

    Article  Google Scholar 

  184. Zidan M A, Fahmy H A H, Hussain M M, et al. Memristor-based memory: the sneak paths problem and solutions. Micro-electron J, 2013, 44: 176–183

    Google Scholar 

  185. Fang Y C, Wang Z W, Cheng C D, et al. Investigation of NbOx-based volatile switching device with self-rectifying characteristics. Sci China Inf Sci, 2019, 62: 229401

    Article  Google Scholar 

  186. Sun P, Lu N, Li L, et al. Thermal crosstalk in 3-dimensional RRAM crossbar array. Sci Rep, 2015, 5: 13504

    Article  Google Scholar 

  187. Kim W, Rösgen B, Breuer T, et al. Nonlinearity analysis of TaOx redox-based RRAM. Microelectron Eng, 2016, 154: 38–41

    Article  Google Scholar 

  188. Wang Z, Kang J, Yu Z, et al. Modulation of nonlinear resistive switching behavior of a TaOx-based resistive device through interface engineering. Nanotechnology, 2017, 28: 055204

    Article  Google Scholar 

  189. Linn E, Rosezin R, Kügeler C, et al. Complementary resistive switches for passive nanocrossbar memories. Nat Mater, 2010, 9: 403–406

    Article  Google Scholar 

  190. Huang Y, Huang R, Pan Y, et al. A new dynamic selector based on the bipolar RRAM for the crossbar array application. IEEE Trans Electron Devices, 2012, 59: 2277–2280

    Article  Google Scholar 

  191. Yu M, Fang Y, Wang Z, et al. Self-selecodulation of TaOx resistive switching random access memory with bottom electrode of highly doped Si. J Appl Phys, 2016, 119: 195302

    Article  Google Scholar 

  192. Wang Z, Kang J, Bai G, et al. Self-selective resistive device with hybrid switching mode for passive crossbar memory application. IEEE Electron Device Lett, 2020, 41: 1009–1012

    Article  Google Scholar 

  193. Dönges S A, Khatib O, O’Callahan B T, et al. Ultrafast nanoimaging of the photoinduced phase transition dynamics in VO2. Nano Lett, 2016, 16: 3029–3035

    Article  Google Scholar 

  194. Wang Z, Rao M, Midya R, et al. Threshold switching of Ag or Cu in dielectrics: materials, mechanism, and applications. Adv Funct Mater, 2018, 28: 1704862

    Article  Google Scholar 

  195. Chen Q, Lin M, Wang Z, et al. Low power parylene-based memristors with a graphene barrier layer for flexible electronics applications. Adv Electron Mater, 2019, 5: 1800852

    Article  Google Scholar 

  196. Chi P, Li S, Xu C, et al. PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. ACM SIGARCH Comput Archit News, 2016, 44: 27–39

    Article  Google Scholar 

  197. Chen Y H, Krishna T, Emer J S, et al. Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE J Solid-State Circ, 2017, 52: 127–138

    Article  Google Scholar 

  198. Manukian H, Traversa F L, Di Ventra M. Accelerating deep learning with memcomputing. Neural Networks, 2019, 110: 1–7

    Article  MATH  Google Scholar 

  199. Krogh A. What are artificial neural networks? Nat Biotechnol, 2008, 26: 195–197

    Article  Google Scholar 

  200. Krenker A, Bešter J, Kos A. Introduction to the artificial neural networks. In: Artificial Neural Networks: Methodological Advances and Biomedical Applications. Rijeka: InTech, 2011. 1–18

    Google Scholar 

  201. Minsky M, Papert S A. Perceptrons: An Introduction to Computational Geometry. Cambridge: MIT Press, 2017

    Book  MATH  Google Scholar 

  202. Sutskever I, Martens J, Hinton G E. Generating text with recurrent neural networks. In: Proceedings of International Conference on Machine Learning, 2011

  203. Schuster M, Paliwal K K. Bidirectional recurrent neural networks. IEEE Trans Signal Process, 1997, 45: 2673–2681

    Article  Google Scholar 

  204. Abdel-Hamid O, Deng L, Yu D. Exploring convolutional neural network structures and optimization techniques for speech recognition. Interspeech. 2013, 11: 73–75

    Google Scholar 

  205. Dumoulin V, Visin F. A guide to convolution arithmetic for deep learning. 2016. ArXiv:1603.07285

  206. Yao P, Wu H, Gao B, et al. Face classification using electronic synapses. Nat Commun, 2017, 8: 15199

    Article  Google Scholar 

  207. Li C, Belkin D, Li Y, et al. Efficient and self-adaptive in-situ learning in multilayer memristor neural networks. Nat Commun, 2018, 9: 2385

    Article  Google Scholar 

  208. Ambrogio S, Narayanan P, Tsai H, et al. Equivalent-accuracy accelerated neural-network training using analogue memory. Nature, 2018, 558: 60–67

    Article  Google Scholar 

  209. Wang Z, Zheng Q, Kang J, et al. Self-activation neural network based on self-selective memory device with rectified multilevel states. IEEE Trans Electron Dev, 2020, 67: 4166–4171

    Article  Google Scholar 

  210. Zheng Q, Wang Z, Gong N, et al. Artificial neural network based on doped HfO2 ferroelectric capacitors with multilevel characteristics. IEEE Electron Dev Lett, 2019, 40: 1309–1312

    Article  Google Scholar 

  211. Kang J, Yu Z, Wu L, et al. Time-dependent variability in RRAM-based analog neuromorphic system for pattern recognition. In: Proceedings of IEEE International Electron Devices Meeting, 2017. 1–4

  212. Yu Z, Wang Z, Kang J, et al. Early-stage fluctuation in low-power analog resistive memory: impacts on neural network and mitigation approach. IEEE Electron Dev Lett, 2020, 41: 940–943

    Article  Google Scholar 

  213. Boureau Y L, Ponce J, LeCun Y. A theoretical analysis of feature pooling in visual recognition. In: Proceedings of International Conference on Machine Learning, 2010. 111–118

  214. Wang Z, Li C, Lin P, et al. In situ training of feed-forward and recurrent convolutional memristor networks. Nat Mach Intell, 2019, 1: 434–442

    Article  Google Scholar 

  215. Yao P, Wu H, Gao B, et al. Fully hardware-implemented memristor convolutional neural network. Nature, 2020, 577: 641–646

    Article  Google Scholar 

  216. Li C, Wang Z, Rao M, et al. Long short-term memory networks in memristor crossbar arrays. Nat Mach Intell, 2019, 1: 49–57

    Article  Google Scholar 

  217. Wang Y, Yu L, Wu S, et al. Memristor-based biologically plausible memory based on discrete and continuous attractor networks for neuromorphic systems. Adv Intell Syst, 2020, 2: 2000001

    Article  Google Scholar 

  218. Yang K, Duan Q, Wang Y, et al. Transiently chaotic simulated annealing based on intrinsic nonlinearity of memristors for efficient solution of optimization problems. Sci Adv, 2020, 6: eaba9901

    Article  Google Scholar 

  219. Cai F, Kumar S, van Vaerenbergh T, et al. Power-efficient combinatorial optimization using intrinsic noise in memristor Hopfield neural networks. Nat Electron, 2020, 3: 409–418

    Article  Google Scholar 

  220. Lu J, Wu Z, Zhang X, et al. Quantitatively evaluating the effect of read noise in memristive Hopfield network on solving traveling salesman problem. IEEE Electron Dev Lett, 2020, 41: 1688–1691

    Article  Google Scholar 

  221. Ghosh-dastidar S, Adeli H. Spiking neural networks. Int J Neur Syst, 2009, 19: 295–308

    Article  Google Scholar 

  222. Wade J J, McDaid L J, Santos J A, et al. SWAT: a spiking neural network training algorithm for classification problems. IEEE Trans Neural Netw, 2010, 21: 1817–1830

    Article  Google Scholar 

  223. Xiang Y, Huang P, Han R, et al. Efficient and robust spike-driven deep convolutional neural networks based on NOR flash computing array. IEEE Trans Electron Dev, 2020, 67: 2329–2335

    Article  Google Scholar 

  224. Bao L, Wang Z, Yu Z, et al. Rotational pattern recognition by spiking correlated neural network based on dualgated MoS2 neuristor. Adv Intell Syst, 2020, 2: 2000102

    Article  Google Scholar 

  225. Wang Z, Joshi S, Savel’ev S, et al. Fully memristive neural networks for pattern classification with unsupervised learning. Nat Electron, 2018, 1: 137–145

    Article  Google Scholar 

  226. Zhang X M, Lu J, Wang Z R, et al. Hybrid memristor-CMOS neurons for in-situ learning in fully hardware memristive spiking neural networks. Sci Bull, 2021, 66: 1624–1633

    Article  Google Scholar 

  227. Duan Q, Jing Z, Zou X, et al. Spiking neurons with spatiotemporal dynamics and gain modulation for monolithically integrated memristive neural networks. Nat Commun, 2020, 11: 1–13

    Article  Google Scholar 

  228. Zhang X, Wang Z, Song W, et al. Experimental demonstration of conversion-based SNNs with 1T1R Mott neurons for neuromorphic inference. In: Proceedings of IEEE International Electron Devices Meeting, 2019. 1–4

  229. Zhang X, Wu Z, Lu J, et al. Fully memristive SNNs with temporal coding for fast and low-power edge computing. In: Proceedings of IEEE International Electron Devices Meeting, 2020. 1–4

  230. Dang B, Liu K, Zhu J, et al. Stochastic neuron based on IGZO Schottky diodes for neuromorphic computing. APL Mater, 2019, 7: 071114

    Article  Google Scholar 

  231. Borghetti J, Snider G S, Kuekes P J, et al. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature, 2010, 464: 873–876

    Article  Google Scholar 

  232. Siemon A, Breuer T, Aslam N, et al. Realization of boolean logic functionality using redox-based memristive devices. Adv Funct Mater, 2015, 25: 6414–6423

    Article  Google Scholar 

  233. Linn E, Rosezin R, Tappertzhofen S, et al. Beyond von Neumann-logic operations in passive crossbar arrays alongside memory operations. Nanotechnology, 2012, 23: 305205

    Article  Google Scholar 

  234. Xu L, Yuan R, Zhu Z, et al. Memristor-based efficient in-memory logic for cryptologic and arithmetic applications. Adv Mater Technol, 2019, 4: 1900212

    Article  Google Scholar 

  235. Yuan R, Ma M, Xu L, et al. Efficient 16 Boolean logic and arithmetic based on bipolar oxide memristors. Sci China Inf Sci, 2020, 63: 202401

    Article  Google Scholar 

  236. Damiani E, Di Vimercati S D C, Samarati P. New paradigms for access control in open environments. In: Proceedings of IEEE International Symposium on Signal Processing & Information Technology, 2005. 540–545

  237. Sadeghi A R, Naccache D. Towards Hardware-Intrinsic Security. Berlin: Springer, 2010

    Book  MATH  Google Scholar 

  238. Konstantinou C, Maniatakos M, Saqib F, et al. Cyber-physical systems: a security perspective. In: Proceedings of the 20th IEEE European Test Symposium (ETS), 2015. 1–8

  239. Yu M D, Sowell R, Singh A, et al. Performance metrics and empirical results of a PUF cryptographic key generation ASIC. In: Proceedings of IEEE International Symposium on Hardware-oriented Security & Trust, 2012. 108–115

  240. Suh G E, Devadas S. Physical unclonable functions for device authentication and secret key generation. In: Proceedings of the 44th ACM/IEEE Design Automation Conference, 2007. 9–14

  241. Holcomb D E, Burleson W P, Fu K. Power-up SRAM State as an identifying fingerprint and source of true random numbers. IEEE Trans Comput, 2009, 58: 1198–1210

    Article  MATH  Google Scholar 

  242. Gao L, Chen P Y, Liu R, et al. Physical unclonable function exploiting sneak paths in resistive cross-point array. IEEE Trans Electron Dev, 2016, 63: 3109–3115

    Article  Google Scholar 

  243. Nili H, Adam G C, Hoskins B, et al. Hardware-intrinsic security primitives enabled by analogue state and nonlinear conductance variations in integrated memristors. Nat Electron, 2018, 1: 197–202

    Article  Google Scholar 

  244. Jiang H, Li C, Zhang R, et al. A provable key destruction scheme based on memristive crossbar arrays. Nat Electron, 2018, 1: 548–554

    Article  Google Scholar 

  245. Gaba S, Sheridan P, Zhou J, et al. Stochastic memristive devices for computing and neuromorphic applications. Nanoscale, 2013, 5: 5872–5878

    Article  Google Scholar 

  246. Jiang H, Belkin D, Savel’ev S E, et al. A novel true random number generator based on a stochastic diffusive memristor. Nat Commun, 2017, 8: 882

    Article  Google Scholar 

  247. Hamming R W. Error detecting and error correcting codes. Bell Syst Tech J, 1950, 29: 147–160

    Article  MATH  Google Scholar 

  248. Mstafa R J, Elleithy K M. A highly secure video steganography using Hamming code (7, 4). In: Proceedings of IEEE Long Island Systems, Applications and Technology (LISAT) Conference, 2014. 1–6

  249. Sun X, Zhang T, Cheng C, et al. A memristor-based in-memory computing network for hamming code error correction. IEEE Electron Device Lett, 2019, 40: 1080–1083

    Article  Google Scholar 

  250. Ben-Romdhane M, Graba T, Danger J L, et al. Design methodology of an ASIC TRNG based on an open-loop delay chain. In: Proceedings of IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013. 1–4

  251. Zhang T, Yin M, Xu C, et al. High-speed true random number generation based on paired memristors for security electronics. Nanotechnology, 2017, 28: 455202

    Article  Google Scholar 

  252. Yu S, Guan X, Wong H S P. On the stochastic nature of resistive switching in metal oxide RRAM: physical modeling, Monte Carlo simulation, and experimental characterization. In: Proceedings of International Electron Devices Meeting, 2011. 1–4

  253. Dang B, Sun J, Zhang T, et al. Physically transient true random number generators based on paired threshold switches enabling Monte Carlo method applications. IEEE Electron Device Lett, 2019, 40: 1096–1099

    Article  Google Scholar 

  254. Xue Y Y, Wang Z J, Chen W, et al. Modeling dark signal of CMOS image sensors irradiated by reactor neutron using Monte Carlo method. Sci China Inf Sci, 2018, 61: 062405

    Article  Google Scholar 

Download references

Acknowledgements

This work was supported by National Key R&D Program of China (Grant No. 2017YFA0207600), National Natural Science Foundation of China (Grant Nos. 61925401, 92064004, 61927901), the Project supported by PKU-Baidu Fund (Grant Nos. 2019BD002, 2020BD010), and the 111 Project (Grant No. B18001). Yuchao YANG acknowledges the support from the Fok Ying-Tong Education Foundation, Beijing Academy of Artificial Intelligence (BAAI), and the Tencent Foundation through the XPLORER PRIZE.

Author information

Authors and Affiliations

Authors

Corresponding authors

Correspondence to Xiaoqin Yan, Yuchao Yang or Ru Huang.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Cheng, C., Tiw, P.J., Cai, Y. et al. In-memory computing with emerging nonvolatile memory devices. Sci. China Inf. Sci. 64, 221402 (2021). https://doi.org/10.1007/s11432-021-3327-7

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s11432-021-3327-7

Keywords

Navigation