Skip to main content
SpringerLink
Log in

Co-optimization strategy between array operation and weight mapping for flash computing arrays to achieve high computing efficiency and accuracy

  • Letter
  • Published:
Science China Information Sciences Aims and scope Submit manuscript

Conclusion

In this study, we propose a co-optimization method of array operation and weight mapping for flash computing arrays to improve computing efficiency and accuracy. The proposed co-optimization can minimize the required computing periods to improve computing efficiency and can maximally decrease the IBLs to alleviate the impact of interconnect resistance. The results show the computing speed is improved by 2x and the accuracy loss induced by the interconnect resistance is maximally reduced to 62%, compared to the conventional method.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

References

  1. Yu S M. Neuro-inspired computing with emerging nonvolatile memorys. Proc IEEE, 2018, 106: 260–285

    Article  Google Scholar 

  2. Lin Y Y, Lee F M, Lee M H, et al. A novel voltage-accumulation vector-matrix multiplication architecture using resistor-shunted floating gate flash memory device for low-power and high-density neural network applications. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2018. 39–42

  3. Malavena G, Spinelli A S, Compagnoni C M. Implementing spike-timing-dependent plasticity and unsupervised learning in a mainstream NOR flash memory array. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2018. 35–38

  4. Han R Z, Xiang Y C, Huang P, et al. Flash memory array for efficient implementation of deep neural networks. Adv Intell Syst, 2021, 3: 2000161

    Article  Google Scholar 

  5. Xiang Y C, Huang P, Yang H Z, et al. Storage reliability of multi-bit flash oriented to deep neural network. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2019. 919–922

  6. International Technology Roadmap for Semiconductors (ITRS). 2015. http://www.semiconductors.org/resources/2015-international-technology-roadmap-for-semiconductors-itrs/

Download references

Acknowledgements

This work was supported by National Key Research and Development (Grant Nos. 2018YFE0100800, 2019YFB2205100), National Nature Science Foundation of China (Grant No. 61841404), and the 111 project (Grant No. B18001).

Author information

Authors and Affiliations

  1. Institute of Microelectronics, Peking University, Beijing, 100871, China

    Guihai Yu, Peng Huang, Runze Han, Lixia Han, Xiaoyan Liu & Jinfeng Kang

Authors
  1. Guihai Yu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Peng Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Runze Han
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Lixia Han
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Xiaoyan Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Jinfeng Kang
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding authors

Correspondence to Peng Huang or Jinfeng Kang.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Yu, G., Huang, P., Han, R. et al. Co-optimization strategy between array operation and weight mapping for flash computing arrays to achieve high computing efficiency and accuracy. Sci. China Inf. Sci. 66, 129403 (2023). https://doi.org/10.1007/s11432-021-3381-3

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s11432-021-3381-3

Search

Navigation