Conclusion
The comprehensive studies aimed at the interplay between the quantum confinement effect and device statistical variability among process design of experiments for sub-5 nm NSTs have been presented and analyzed through strictly calibrated TCAD simulation platform for the first time. The impact of quantum confinement variation on the key performance parameters of NSTs with different channel geometry structures also have been studied. It is found that the NSTs with the optimized nanosheet thickness of approximate 4 nm have the best key figures of merit. After considering the interplay between the quantum confinement and statistical variability, MGG as the dominant statistical variability source brings the largest threshold voltage fluctuation and the MGG-induced variability can be suppressed with the average grain size reduction, but SER can also cause the comparable threshold voltage variation for 3 nm thick NSTs mainly due to the strong quantum confinement variation. Meanwhile the SER-induced variability can also be suppressed by the uniform smooth nanosheet edges.
References
Loubet N, Hook T, Montanini P, et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond Fin-FET. In: Proceedings of Symposium on VLSI Technology, Kyoto, 2017. T230–T231
Wang X, Brown A R, Idris N, et al. Statistical threshold-voltage variability in scaled decananometer bulk HKMG MOSFETs: a full-scale 3-D simulation scaling study. IEEE Trans Electron Dev, 2011, 58: 2293–2301
Wang X, Cheng B, Brown A R, et al. Interplay between process-induced and statistical variability in 14-nm CMOS technology double-gate SOI FinFETs. IEEE Trans Electron Dev, 2013, 60: 2485–2492
Rawat A, Gorad A, Ganguly U. Analytical estimation of LER-like variability in GAA nano-sheet transistors. In: Proceedings of International Symposium on VLSI Technology, Systems and Application, Taipei, 2019. 1–2
Ancona M G. Density-gradient theory: a macroscopic approach to quantum confinement and tunneling in semiconductor devices. J Comput Electron, 2011, 10: 65–97
Park J, Lee H, Oh S, et al. Design for variation-immunity in sub-10-nm stacked-nanowire FETs to suppress LER-induced random variations. IEEE Trans Electron Devices, 2016, 63: 5048–5054
Acknowledgements
This work was supported in part by National Key Research and Development Program of China (Grant No. 2019YFB2205100), National Natural Science Foundation of China (Grant No. 61841404), and Hubei Key Laboratory of Advanced Memories. The authors thank Professor Asen Asenov from University of Glasgow, UK for fruitful discussions, and thank Synopsys for generous software donation.
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Appendixes A–D. The supporting information is available online at info.scichina.com and link.springer.com. The supporting materials are published as submitted, without typesetting or editing. The responsibility for scientific accuracy and content remains entirely with the authors.
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A Comprehensive Study of Device Variability Of Sub-5nm Nanosheet Transistors and Interplay with Quantum Confinement Variation
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Luo, H., Li, R., Miao, X. et al. A comprehensive study of device variability of sub-5 nm nanosheet transistors and interplay with quantum confinement variation. Sci. China Inf. Sci. 66, 129402 (2023). https://doi.org/10.1007/s11432-021-3399-3
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DOI: https://doi.org/10.1007/s11432-021-3399-3