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An efficient path delay variability model for wide-voltage-range digital circuits

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References

  1. Jooypa H, Dideban D. Impact analysis of statistical variability on the accuracy of a propagation delay time compact model in nano-CMOS technology. J Comput Electron, 2018, 17: 192–204

    Article  Google Scholar 

  2. Liu B, Zhang Z L, Cai H, et al. Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN processing. Sci China Inf Sci, 2022, 65: 149403

    Article  Google Scholar 

  3. Jooypa H, Dideban D. Statistical strategies to reproduce the propagation delay time variability using compact models. IEEE Trans Circ Syst II, 2019, 66: 1880–1884

    Google Scholar 

  4. Ju P J, Zhang H S. Achievable delay margin using LTI control for plants with unstable complex poles. Sci China Inf Sci, 2018, 61: 092203

    Article  MathSciNet  Google Scholar 

  5. Cai M X, Yao R H. A threshold voltage and drain current model for symmetric dual-gate amorphous InGaZnO thin film transistors. Sci China Inf Sci, 2018, 61: 022401

    Article  Google Scholar 

  6. Shan W, Dai W, Zhang C, et al. TG-SPP: a one-transmission-gate short-path padding for wide-voltage-range resilient circuits in 28-nm CMOS. IEEE J Solid-State Circ, 2020, 55: 1422–1436

    Article  Google Scholar 

  7. Alioto M, Scotti G, Trifiletti A. A novel framework to estimate the path delay variability on the back of an envelope via the fan-out-of-4 metric. IEEE Trans Circ Syst I, 2017, 64: 2073–2085

    Google Scholar 

Download references

Acknowledgements

This work was supported by National Natural Science Foundation of China (Grant Nos. 62122021, 62074035), Natural Science Foundation of Jiangsu Province (Grant No. BK20200002), and Fundamental Research Funds for the Central Universities (Grant Nos. 2242021k30031, 2242021k10008).

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Authors and Affiliations

  1. National ASIC System Engineering Research Center, Southeast University, Nanjing, 210096, China

    Weiwei Shan, Yuqiang Cui, Xinning Liu, Peng Cao & Jun Yang

  2. Cadence Design Systems Inc., Nanjing, 210031, China

    Wentao Dai

  3. College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing, 210023, China

    Jingjing Guo

Authors
  1. Weiwei Shan
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  2. Yuqiang Cui
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  3. Wentao Dai
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  4. Xinning Liu
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  5. Jingjing Guo
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  6. Peng Cao
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  7. Jun Yang
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Corresponding author

Correspondence to Xinning Liu.

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Appendix A. The supporting information is available online at info.scichina.com and link.springer.com. The supporting materials are published as submitted. without typesetting or editing. The responsibility for scientific accuracy and content remains entirely with the authors.

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Shan, W., Cui, Y., Dai, W. et al. An efficient path delay variability model for wide-voltage-range digital circuits. Sci. China Inf. Sci. 66, 129401 (2023). https://doi.org/10.1007/s11432-021-3407-2

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  • DOI: https://doi.org/10.1007/s11432-021-3407-2