Skip to main content
SpringerLink
Log in

An ultra-high-density and energy-efficient content addressable memory design based on 3D-NAND flash

  • Research Paper
  • Published:
Science China Information Sciences Aims and scope Submit manuscript

Abstract

In this article, the design of a novel 3D-NAND-based content addressable memory (CAM) consisting of two flash transistors with ultra-high density and low power consumption is proposed for data-intensive computing. Hewlett simulation program with integrated circuit emphasis (HSPICE) of a 3D-NAND-based CAM array is performed to study the functionality and properties of the presented CAM design, and the results indicate that the energy consumption is 0.196 fJ/bit/search. The cell density of a 16-layer 3D-NAND flash is 157 times higher than CAMs based on conventional static random access memory. Furthermore, to exploit the multibit storage property of 3D-NAND flash, we also propose a multilevel CAM design, which significantly boosts the cell density and expands the functionality. As a proof-of-concept illustration, we take a 4-level CAM to successfully implement the search operation. Furthermore, the impacts of 3D-NAND layers and parasitic effects on the performance of the proposed CAM design are also discussed.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Thangam M S, Vijayalakshmi M. Data-intensive computation offloading using fog and cloud computing for mobile devices applications. In: Proceedings of International Conference on Smart Systems and Inventive Technology, Tirunelveli, 2018. 547–550

  2. Jonathan A, Ryden M, Oh K, et al. Nebula: distributed edge cloud for data intensive computing. IEEE Trans Parallel Distrib Syst, 2017, 28: 3229–3242

    Article  Google Scholar 

  3. Zhang X Y, Liu C L, Suen C Y. Towards robust pattern recognition: a review. Proc IEEE, 2020, 108: 894–922

    Article  Google Scholar 

  4. Ye Q, Doermann D. Text detection and recognition in imagery: a survey. IEEE Trans Pattern Anal Mach Intell, 2014, 37: 1480–1500

    Article  Google Scholar 

  5. Nielen L, Siemon A, Tappertzhofen S, et al. Study of memristive associative capacitive networks for CAM applications. IEEE J Emerg Sel Top Circ Syst, 2015, 5: 153–161

    Article  Google Scholar 

  6. Zheng L, Shin S, Steve Kang S M. Memristor-based ternary content addressable memory (mTCAM) for data-intensive computing. Semicond Sci Technol, 2014, 29: 104010

    Article  Google Scholar 

  7. Huang P T, Lai S L, Chuang C T, et al. 0.339 fJ/bit/search energy-efficient TCAM macro design in 40 nm LP CMOS. In: Proceedings of Asian Solid-State Circuits Conference, KaoHsiung, 2014. 129–132

  8. Pagiamtzis K, Sheikholeslami A. Content-addressable memory (CAM) circuits and architectures: a tutorial and survey. IEEE J Solid-State Circ, 2006, 41: 712–727

    Article  Google Scholar 

  9. El Baraji M, Javerliac V, Prenat G. Towards an ultra-low power, high density and non-volatile ternary cam. In: Proceedings of Non-Volatile Memory Technology Symposium, Pacific Grove, 2008. 1–7

  10. Imani M, Peroni D, Rahimi A, et al. Resistive CAM acceleration for tunable approximate computing. IEEE Trans Emerg Top Comput, 2019, 7: 271–280

    Article  Google Scholar 

  11. Karam R, Puri R, Ghosh S, et al. Emerging trends in design and applications of memory-based computing and content-addressable memories. Proc IEEE, 2015, 103: 1311–1330

    Article  Google Scholar 

  12. Li J, Montoye R, Ishii M, et al. 1 Mb 0.41 µm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing. In: Proceedings of Symposium on VLSI Technology, Kyoto, 2013. 104–105

  13. Han R, Shen W, Huang P, et al. A novel ternary content addressable memory design based on resistive random access memory with high intensity and low search energy. Jpn J Appl Phys, 2018, 57: 04FE02

    Article  Google Scholar 

  14. Chen B, Zhang Y, Liu W, et al. Ge-based asymmetric RRAM enable 8F2 content addressable memory. IEEE Electron Device Lett, 2018, 39: 1294–1297

    Article  Google Scholar 

  15. Zheng L, Shin S, Lloyd S, et al. RRAM-based TCAMs for pattern search. In: Proceedings of International Symposium on Circuits and Systems, Montreal, 2016. 1382–1385

  16. Grossi A, Vianello E, Zambelli C, et al. Experimental investigation of 4-kb RRAM arrays programming conditions suitable for TCAM. IEEE Trans VLSI Syst, 2018, 26: 2599–2607

    Article  Google Scholar 

  17. Yin X, Li C, Huang Q, et al. FeCAM: a universal compact digital and analog content addressable memory using ferroelectric. IEEE Trans Electron Dev, 2020, 67: 2785–2792

    Article  Google Scholar 

  18. Tan A J, Chatterjee K, Zhou J, et al. Experimental demonstration of a ferroelectric HfO -based content addressable memory cell. IEEE Electron Device Lett, 2019, 41: 240–243

    Article  Google Scholar 

  19. Ni K, Yin X, Laguna A F, et al. Ferroelectric ternary content-addressable memory for one-shot learning. Nat Electron, 2019, 2: 521–529

    Article  Google Scholar 

  20. Wang C, Zhang D, Zeng L, et al. Design of magnetic non-volatile TCAM with priority-decision in memory technology for high speed, low power, and high reliability. IEEE Trans Circ Syst I, 2020, 67: 464–474

    Google Scholar 

  21. Gupta M K, Hasan M. Robust high speed ternary magnetic content addressable memory. IEEE Trans Electron Dev, 2015, 62: 1163–1169

    Article  Google Scholar 

  22. Xu W, Zhang T, Chen Y. Design of spin-torque transfer magnetoresistive RAM and CAM/TCAM with high sensing and search speed. IEEE Trans VLSI Syst, 2009, 18: 66–74

    Article  Google Scholar 

  23. Miwa T, Yamada H, Hirota Y, et al. A 1 Mb 5-transistor/bit non-volatile CAM based on flash-memory technologies. In: Proceedings of International Solid-State Circuits Conference, San Francisco, 1996. 40–41

  24. Kramer A, Canegallo R, Chinosi M, et al. 55 GCPS CAM using 5b analog flash. In: Proceedings of International Solid-State Circuits Conference, San Francisco, 1997. 44–45

  25. Fedorov V V, Abusultan M, Khatri S P. An area-efficient ternary CAM design using floating gate transistors. In: Proceedings of International Conference on Computer Design, Seoul, 2014. 55–60

  26. Wang F, Feng Y, Zhan X, et al. Implementation of data search in multi-level NAND flash memory by complementary storage scheme. IEEE Electron Dev Lett, 2020, 41: 1189–1192

    Article  Google Scholar 

  27. Suh K D, Suh B H, Lim Y H, et al. A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme. IEEE J Solid-State Circ, 1995, 30: 1149–1156

    Article  Google Scholar 

  28. Kang D, Kim M, Jeon S C, et al. A 512 Gb 3-bit/Cell 3D 6th-Generation V-NAND flash memory with 82 MB/s write throughput and 1.2 Gb/s interface. In: Proceedings of International Solid-State Circuits Conference, San Francisco, 2019. 216–218

  29. Yang H Z, Huang P, Han R Z, et al. A novel high-density and low-power ternary content addressable memory design based on 3D NAND flash. In: Proceedings of Silicon Nanoelectronics Workshop, Honolulu, 2020. 29–30

  30. Lue H T, Du P Y, Chen W C, et al. A 128 Gb (MLC)/192 Gb (TLC) single-gate vertical channel (SGVC) architecture 3D NAND using only 16 layers with robust read disturb, long-retention and excellent scaling capability. In: Proceedings of International Electron Devices Meeting, San Francisco, 2017

  31. Wang P, Xu F, Wang B, et al. Three-dimensional NAND flash for vector-matrix multiplication. IEEE Trans VLSI Syst, 2018, 27: 988–991

    Article  Google Scholar 

  32. Lee S H, Kwon D W, Kim S, et al. Investigation of transient current characteristics with scaling-down poly-Si body thickness and grain size of 3D NAND flash memory. Solid-State Electron, 2019, 152: 41–45

    Article  Google Scholar 

  33. Cho J, Kang D C, Park J, et al. A 512Gb 3b/cell 7th-generation 3D-NAND flash memory with 184 MB/s write throughput and 2.0 Gb/s interface. In: Proceedings of International Solid-State Circuits Conference, San Francisco, 2021. 426–428

  34. Lee S, Kim C, Kim M, et al. A 1 Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12 MB/s program throughput. In: Proceedings of International Solid-State Circuits Conference, San Francisco, 2018. 340–342

  35. Cai Y, Haratsch E F, Mutlu O, et al. Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling. In: Proceedings of Design, Automation & Test in Europe Conference & Exhibition, Grenoble, 2013. 1285–1290

  36. Arsovski I, Hebig T, Dobson D, et al. A 32 nm 0.58-fJ/Bit/search 1-GHz ternary content addressable memory compiler using silicon-aware early-predict late-correct sensing with embedded deep-trench capacitor noise mitigation. IEEE J Solid-State Circ, 2013, 48: 932–939

    Article  Google Scholar 

  37. Siau C, Kim K H, Lee S, et al. A 512 Gb 3-bit/cell 3D flash memory on 128-wordline-layer with 132 MB/s write performance featuring circuit-under-array technology. In: Proceedings of International Solid-State Circuits Conference, San Francisco, 2019. 218–220

  38. Tseng P H, Lee F M, Lin Y H, et al. In-memory-searching architecture based on 3D-NAND technology with ultra-high parallelism. In: Proceedings of International Electron Devices Meeting, San Francisco, 2020

  39. Wang K L, Du G, Lun Z Y, et al. Modeling of program Vth distribution for 3-D TLC NAND flash memory. Sci China Inf Sci, 2019, 62: 042401

    Article  Google Scholar 

  40. Pedretti G, Graves C E, Serebryakov S, et al. Tree-based machine learning performed in-memory with memristive analog CAM. Nat Commun, 2021, 12: 1

    Article  Google Scholar 

  41. Kazemi A, Sharifi M M, Laguna A F, et al. In-memory nearest neighbor search with FeFET multi-bit content-addressable memories. In: Proceedings of Design, Automation & Test in Europe Conference & Exhibition, Grenoble, 2021. 1084–1089

  42. Li H T, Chen W C, Levy A, et al. One-shot learning with memory-augmented neural networks using a 64-kbit, 118 GOPS/W RRAM-based non-volatile associative memory. In: Proceedings of Symposium on VLSI Technology, Kyoto, 2021. 1–2

Download references

Acknowledgements

This work was supported in part by National Key Research and Development Program of China (Grant Nos. 2019YFB2205100, 2018YFA0701500), National Natural Science Foundation of China (Grant No. 62034006), and 111 Project Program (Grant No. B18001).

Author information

Authors and Affiliations

  1. School of Integrated Circuits, Peking University, Beijing, 100871, China

    Haozhang Yang, Peng Huang, Runze Han, Xiaoyan Liu & Jinfeng Kang

Authors
  1. Haozhang Yang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Peng Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Runze Han
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Xiaoyan Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Jinfeng Kang
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding authors

Correspondence to Peng Huang or Jinfeng Kang.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Yang, H., Huang, P., Han, R. et al. An ultra-high-density and energy-efficient content addressable memory design based on 3D-NAND flash. Sci. China Inf. Sci. 66, 142402 (2023). https://doi.org/10.1007/s11432-021-3502-4

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s11432-021-3502-4

Keywords

Search

Navigation