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Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing

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Abstract

This paper presents novel algorithmic and architectural solutions for real-time and power-efficient enhancement of images and video sequences. A programmable class of Retinex-like filters, based on the separation of the illumination and reflectance components, is proposed. The dynamic range of the input image is controlled by applying a suitable non-linear function to the illumination, while the details are enhanced by processing the reflectance. An innovative spatially recursive rational filter is used to estimate the illumination. Moreover, to improve the visual quality results of two-branch Retinex operators when applied to videos, a novel three-branch technique is proposed which exploits both spatial and temporal filtering. Real-time implementation is obtained by designing an Application Specific Instruction-set Processor (ASIP). Optimizations are addressed at algorithmic and architectural levels. The former involves arithmetic accuracy definition and linearization of non-linear operators; the latter includes customized instruction set, dedicated memory structure, adapted pipeline, bypasses, custom address generator, and special looping structures. The ASIP is synthesized in standard-cells CMOS technology and its performances are compared to known Digital signal processor (DSP) implementations of real-time Retinex filters. As a result of the comparison, the proposed algorithmic/architectural design outperforms state-of-art Retinex-like operators achieving the best trade-off between power consumption, flexibility, and visual quality.

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Notes

  1. About 2-branch version for still gray-scale images in Sect. 2 with the enhancements discussed in Sects 3.1 and 3.2.

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Acknowledgments

The contribution to the LISA design of M. Cassiano from University of Pisa, now with STMicroelectronics, Italy, and D. Kammler, E. M. Witte, O. Schliebusch, G. Ascheid, R. Leupers and H. Meyr from ISS, RWTH Aachen University, Germany, is gratefully acknowledged. The work performed at the University of Trieste was partially supported by a research grant of the Regione Autonoma Friuli—Venezia Giulia. The work performed at the University of Pisa was partially supported by the Network of Excellence in Wireless COMmunications (NEWCOM).

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Authors and Affiliations

  1. Dipartimento Ingegneria della Informazione, University of Pisa, via Caruso 16, 56122, Pisa, Italy

    Sergio Saponara & Luca Fanucci

  2. Dipartimento Elettrotecnica, Elettronica, Informatica, University of Trieste, via Valerio 10, 34127, Trieste, Italy

    Stefano Marsi & Giovanni Ramponi

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  1. Sergio Saponara
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  2. Luca Fanucci
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  3. Stefano Marsi
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  4. Giovanni Ramponi
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Correspondence to Sergio Saponara.

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Saponara, S., Fanucci, L., Marsi, S. et al. Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing. J Real-Time Image Proc 1, 267–283 (2007). https://doi.org/10.1007/s11554-007-0027-z

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  • DOI: https://doi.org/10.1007/s11554-007-0027-z

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