Skip to main content
SpringerLink
Log in

A real-time H.264/AVC VLSI encoder architecture

  • Original Research Paper
  • Published:
Journal of Real-Time Image Processing Aims and scope Submit manuscript

Abstract

Evolving applications related to video technologies require video encoder and decoder implemented with low cost and achieving real-time performance. In order to meet this demand and targeting especially the applications imposing low VLSI area requirements, the present paper describes a VLSI H.264/AVC encoder architecture performing at real-time. The encoder uses a pipeline architecture and all the modules have been optimized with respect to the VLSI cost. The encoder design complies with the reference software encoder of the standard, follows the baseline profile level 3.0 and it constitutes an IP-core and/or an efficient stand-alone solution. The architecture operates at a maximum frequency of 100 MHz and achieves maximum throughput of 30 frames/s with frame size 1,024 × 768. Results and performance measurements of the entire encoder have been validated on FPGA and VLSI 0.18 μm occupying a total area of 3.9 mm2.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

References

  1. ITU-T: SERIES H: Audiovisual and Multimedia Systems: Infrastructure of Audiovisual Services—Coding of Moving Video. ITU-T Rec. H.264, May 2003

  2. Sullivan, G., Topiwala, P., Luthra, A.: The H.264/AVC Advanced Video Coding Standard: Overview and Introduction to the Fidelity Range Extensions. Digital Image Processing XXVII, SPIE 04, August 2004

  3. ITU-T: Video coding for low bit rate communication. ITU-T Rec. H.263, v1: November 1995, v2: January 1998, v3: November 2000

  4. ISO/IEC JTC 1: Coding of audio-visual objects—Part 2: Visual. ISO/IEC 14496-2 (MPEG-4 Part 2), January 1999 (with several subsequent amendments and corrigenda)

  5. H.261/3 and MPEG-4 Video Encoder IP Core. http://www.4i2i.com

  6. Chen, T.C., Huang, Y.W., Chen, L.G.: Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture. Circuits Syst. ISCAS ’04 2, 273–276 (2004)

    Article  Google Scholar 

  7. Amer, I., Badawy, W., Jullien, G.: Hardware prototyping for the H.264 4 × 4 transformation. Acoust. Speech Signal Process. ICASSP ’04 5, 77–80 (2004)

    Google Scholar 

  8. Lee, J.H., Lee, N.S.: Variable block size motion estimation algorithm and its hardware architecture for H.264/AVC. Circuits Syst. ISCAS ’04 3, 741–744 (2004)

    Google Scholar 

  9. Huang, Y.W., Hsieh, B.Y., Chen, T.C., Chen, L.G.: Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder. IEEE Trans. Circuits Syst. Video Technol. 15(3), 378–401 (2005)

    Article  Google Scholar 

  10. Huang, Y.W., Chen, T.W., Hsieh, B.Y., Wang, T.C., Chang, T.H., Chen, L.G.: Architecture design for deblocking filter in H.264/JVT/AVC. Multimedia Expo ICME ’03 1, 693–696 (2003)

    Google Scholar 

  11. Nakayama, H., et al.: An MPEG-4 video LSI with an error resilient codec core based on a fast motion estimation algorithm. IEEE Solid State Circuits Conf. 1, 368–369 (2002)

    Google Scholar 

  12. Hashimoto, T., et al.: A 90 mW MPEG4 video codec LSI with the capability for core profile. IEEE Solid State Circuits Conf., pp. 140–141 (2001). http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=912577

  13. Chen, T.C., Lian, C.-Jr., Chen, L.-G.: Hardware architecture design of an H.264/AVC video codec. Design automation, 2006. Asia South Pac. Conf. 8, 24–27 (2006)

    Google Scholar 

  14. JM: H.264/AVC reference encoder version 9.6. http://iphome.hhi.de/suehring/tml/

  15. Schuster, G.M., Katsaggelos, A.K.: Fast and efficient mode and quantizer selection in the rate distortion sense for H.263. In: Proceedings of the SPIE Conference on Visual Communications and Image Processing, May 1996

  16. Ortega, A., Ramchandran, K.: Rate-distorion methods for image and video compression: an overview. IEEE Signal Process Mag., November 1998

  17. Richardson, I.E.G.: H.264 and MPEG-4 Video Compression. Wiley, New York (2003)

  18. Lee, K.B., Chang, Y.C., Chin, H.Y., Hsu, H.C., Jen, C.W.: A bandwidth and memory efficient MPEG-4 shape encoder. IEEE Des. Automat. Conf., 525–526 (2004). http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1337631

  19. Shih, S., Chang, C., Lin, Y.: A near optimal deblocking filter for H.264 advanced video coding. Conf. Asia South Pac. Des. Automat. 170–175 (2006). http://portal.acm.org/citation.cfm?id=1118349#

  20. Dias, T., Momcilovic, S., Roma, N., Sousa, L.: Adaptive motion estimation processor for autonomous video devices. EURASIP J. Embed. Syst. 2007(1), (2007). http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2007/57234&e=cta

  21. Beric, A., Sethuraman, R., Peters, H., van Meerbergen, J., de Haan, G., Pinto, C.A.: A 27 mW 1.1 mm2 motion estimator for picture-rate up-converter. Proc. 17th Int. Conf. VLSI Des. 17, 1083–1088 (2004)

    Google Scholar 

  22. The Xvid MPEG-4 encoder. http://www.xvid.org

  23. Tourapis, A.M., Au, O.C., Liou, M.L.: Predictive Motion Vector Field Adaptive Search Technique (PMVFAST)—Enhancing Block Based Motion Estimation. In: Proceedings of Visual Communications and Image Processing 2001 (VCIP’01) (2001)

  24. Tourapis, A.M., Au, O.C., Liou, M.L.: Highly efficient predictive zonal algorithms for fast block-matching motion estimation. IEEE Trans. Circuits Syst. Video Technol. 12(10), 934–947 (2002)

    Article  Google Scholar 

Download references

Acknowledgments

This work has supported in part by the PAVET 05-181 project of the Greek General Secretariat for Information Systems.

Author information

Authors and Affiliations

  1. Electronics Laboratory, Department of Physics, National and Kapodistrian University of Athens, Athens, Greece

    K. Babionitakis, G. Lentaris, K. Nakos, D. Reisis & N. Vlassopoulos

  2. Global Digital Technologies S.A., Athens, Greece

    G. Doumenis, G. Georgakarakos & I. Sifnaios

Authors
  1. K. Babionitakis
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. G. Doumenis
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. G. Georgakarakos
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. G. Lentaris
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. K. Nakos
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. D. Reisis
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. I. Sifnaios
    View author publications

    You can also search for this author in PubMed Google Scholar

  8. N. Vlassopoulos
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to D. Reisis.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Babionitakis, K., Doumenis, G., Georgakarakos, G. et al. A real-time H.264/AVC VLSI encoder architecture. J Real-Time Image Proc 3, 43–59 (2008). https://doi.org/10.1007/s11554-007-0054-9

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11554-007-0054-9

Keywords

Search

Navigation