Skip to main content
SpringerLink
Log in

Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing

  • Special Issue
  • Published:
Journal of Real-Time Image Processing Aims and scope Submit manuscript

Abstract

Technology evolution makes possible the integration of heterogeneous components as programmable elements (processors), hardware dedicated blocks, hierarchical memories and buses. Furthermore, an optimized reconfigurable logic core embedded within a System-on-Chip will associate the performances of dedicated architecture and the flexibility of programmable ones. In order to increase performances, some of the applications are carried out in hardware, using dynamically reconfigurable logic, rather than software, using programmable elements. This approach offers a suitable hardware support to design malleable systems able to adapt themselves to a specific application. This article makes a synthesis of the Ardoise project. The first objective of Ardoise project was to design and to produce a dynamically reconfigurable platform based on commercial FPGAs. The concept of dynamically reconfigurable architecture depends partially on new design methodologies elaboration as well as on the programming environment. The platform architecture was designed to be suitable for real-time image processing. The article outlines mainly the Ardoise tools aspect: development environment and real-time management of the hardware tasks. The proposed methodology is based on a dynamic management of tasks according to an application scenario written using C++ language.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18

Similar content being viewed by others

References

  1. Iseli, C., Sanchez, E.: Spyder: A SURE (SUperscalar and REconfigurable) Processor. The Journal of Supercomuting, vol. 9, no. 3, pp. 231–252. Springer, Netherlands (1995)

  2. Iseli, C.: Spyder: a Reconfigurable Processor Development System. PhD thesis, Ecole Polytechnique Federale de Lausanne, Suisse (1996)

  3. Guermoud, H.: Architectures reconfigurables dynamiquement dediees aux traitements en temps reel des signaux video. PhD thesis, Ecole Faculty of Nancy I, France (1997)

  4. Kalte, H., Porrmann, M., Ruckert, U.: A Prototyping Platform for Dynamically Reconfgurable System on Chip Designs. In: IEEE Workshop Heterogeneous Reconfigurable Systems on Chip, Hamburg (2002)

  5. Porrmann, M., Witkowski, U., Kalte, H., Ruckert, U.: Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator. In: Euromicro Workshop on Parallel, Distributed and Network-based Processing, Gran Canaria Island (2002)

  6. David, R.: Architecture reconfigurable dynamiquement pour applications mobiles. PhD thesis, Université de Rennes, France (2003)

  7. Sassatelli, G.: Systolic Ring: Architectures Reconfigurables Dynamiquement pour les Systèmes sur Puce. PhD thesis, Université Montpellier II, France (2002)

  8. Hartenstein, H.: A decade of reconfigurable computing: a visionary retrospective. In: Proceedings of the conference on Design, automation and test in Europe, DATE’01, Piscataway, NJ (2001)

  9. Ebeling, C., Cronquist, D.C., Franklin, P.: RaPiD - Reconfigurable Pipelined Datapath. In: The 6th International Workshop on Field-Programmable Logic and Applications (1996)

  10. Cherepacha, D., Lewis, D.M.: DP-FPGA: an FPGA architecture optimized for datapath. VLSI Des. 4(4), 329–343 (1996)

    Google Scholar 

  11. Goldstein, S., et al.: PipeRench: A Coprocessor for Streaming multimedia Acceleration. In: Proceedings of the 26th Annual International Symposium on Computer Architecture, pp. 28–39 (1999)

  12. Compton, K., Cooley, J., Knol, S., Hauck, S.: Configuration Relocation and Defragmentation for Run-time Reconfigurable Computing. IEEE Trans. Very Large Scale Integr. Syst. 10(3), 209–220 (2002)

    Article  Google Scholar 

  13. Wigley, G., Kearney, D.: The first real operating system for reconfigurable computers. In: Australasian conference on Computer systems architecture (AustCSAC), pp. 130–137 (2001)

  14. Steiger, C., Walder, H., Platzner, M.: Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. IEEE Trans. Comput. 53(11), 1392–1407 (2004)

    Article  Google Scholar 

  15. Demigny, D., Kessal, L., Bourguiba, R., Boudouani, N.: How to use high speed reconfigurable FPGA for real time image processing? In: Proc. IEEE Conf. on Computer Architecture for Machine Perception, Padova, IEEE Circuit and Systems, pp. 240–246 (2000)

  16. Kessal, L., Abel, N., Demigny, D.: Real-time Image Processing With Dynamically Recongurable Architecture. Real Time Imaging, vol. 9, pp. 297–313. Elsevier, Amsterdam (2003)

  17. Atmel: AT40K FPGA with FreeRAM. Data sheet Atmel Inc (1999)

  18. Kalte, H., Langen, D., Vonnahme, E., Brinkmann, A., Ruckert, U.: Dynamically Reconfigurable System-on-Programmable-Chip. In: Proc of 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing (PDP 2002). Gran Canaria Island (2002)

  19. Xilinx: Virtex-II Platform FPGA Handbook. Data sheet Xilinx Inc (2001)

  20. David, R., Chillet, D., Pillement, S., Sentiyes, O.: A Dynamically Reconfigurable Architecture for Low-power Multimedia Terminals. SoC Design Methodology. pp. 51–62. Kluwer, Dordrecht (2002)

  21. Lamaty, P., Mazar, B., Demigny, D., Kessal, L., Karabernou, M.: Two ASIC for Low and Middle Levels of Real Time Image Processing. SoC Design Methodology. pp. 3–14. Kluwer, Dordrecht (2002)

  22. Torres, L., Bourennane, E.B., Robert, M., Paindavoine, M.: Implantation du detecteur de contours Canny-Deriche optimise sous forme d’un circuit specifique. Traitement du signal, Numero Special. vol. 14, pp. 15–28 (1997)

  23. Quesne, J.F.: Vision robotique : Architectures data-flow pour le traitement des images en temps reel. Thesis, faculty of Paris-Sud, France (1992)

  24. Danne, K., Muehlenbernd, R., Platzner, M.: Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In: Field Programmable Logic and its Applications (FPL) (2006)

  25. Canny, J.F.: A computational approach to edge detection. IEEE Trans. Pattern Anal. Mach. Intell. 8, 679–698 (1986)

    Article  Google Scholar 

  26. Deriche, R.: Using Canny’s criteria to derive a recursively implemented optimal edge detector. Int. J. Compu. Vision 1, 167–187 (1987)

    Article  Google Scholar 

  27. Lorca, F.G.: Filtres recursifs temps reel pour la detection des contours : Optimisation algorithmique et architecturales. Thesis, faculty of Paris-Sud, France (1996)

  28. Kamle, T.: Implantation d’algorithmes de traitement de signaux bi-dimensionnels en flot de données sur Asics et circuits reconfigurables. Thesis, faculty of Paris-Sud, France (1994)

  29. VSI A: Virtual Component Transfer specification/Virtual Component Interface Standard. available online, VSI Alliance, Inc. http://www.vsi.org (2006)

  30. Coussy, P., Casseau, E., Bomel, P., Baganne, A., Martin, E.: A formal method for hardware IP design and integration under I/O and timing constraints. Integr. ACM Trans. Embed. Comput. Syst. 5(1), 29–53 (2006)

    Article  Google Scholar 

  31. Sassatelli, G., Torres, L., Benoit, P., Cambon, G., Robert, M., Caly, J.: Dynamically Reconfigurable Architectures for Digital Signal Processing Applications. SoC Design Methodology. pp. 63–74. Kluwer, Dordrecht (2002)

  32. Abel, N., Kessal, L., Demigny, D.: Design flexibility using FPGA dynamical reconfiguration. In: Proc. International Conference on Image Processing, Singapour, pp. 2821–2824 (2004)

  33. Marescaux, T., Nollet, V., Mignolet, J.Y., Bartic, A., Moffat, W., Avasare, P., Coene, P., Verkest, D., Vernalde, S., Lauwereins, R.: Run-time support for heterogeneous multitasking on reconfigurable SoCs. Integr. VLSI J. 38(1), 107–130 (2004)

    Article  Google Scholar 

  34. Qu, Y., Soininen, J.P., Nurmi, J.: Static scheduling techniques for dependent tasks on dynamically reconfigurable devices. J. Syst. Arch 53(11), 861–876 (2007)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. ETIS/ENSEA, 6 avenue du Ponceau, 95000, Cergy, France

    Lounis Kessal, Nicolas Abel & Si Mahmoud Karabernou

  2. R2D2, Lannion, France

    Didier Demigny

Authors
  1. Lounis Kessal
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Nicolas Abel
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Si Mahmoud Karabernou
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Didier Demigny
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Lounis Kessal.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Kessal, L., Abel, N., Karabernou, S.M. et al. Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing. J Real-Time Image Proc 3, 131–147 (2008). https://doi.org/10.1007/s11554-008-0076-y

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11554-008-0076-y

Keywords

Search

Navigation