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An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

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Abstract

In this paper, an efficient architecture for the Finite Ridgelet Transform (FRIT) suitable for VLSI implementation based on a parallel, systolic Finite Radon Transform (FRAT) and a Haar Discrete Wavelet Transform (DWT) sub-block, respectively is presented. The FRAT sub-block is a novel parametrisable, scalable and high performance core with a time complexity of O(p 2), where p is the block size. Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations are carried out to analyse the performance of the FRIT core developed.

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Authors and Affiliations

  1. Electronic and Computer Engineering, School of Engineering and Design, Brunel University, Howell Building (H-254), West London, UK 

    Shrutisagar Chandrasekaran & Abbes Amira

  2. Department of Electrical and Electronic Engineering Hong Kong, University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong 

    Shi Minghua & Amine Bermak

Authors
  1. Shrutisagar Chandrasekaran
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  2. Abbes Amira
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  3. Shi Minghua
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  4. Amine Bermak
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Correspondence to Abbes Amira.

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Chandrasekaran, S., Amira, A., Minghua, S. et al. An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform. J Real-Time Image Proc 3, 183–193 (2008). https://doi.org/10.1007/s11554-008-0081-1

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  • DOI: https://doi.org/10.1007/s11554-008-0081-1

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