Abstract
Integral imaging is a promising technique for delivering high-quality three-dimensional content. However, the large amounts of data produced during acquisition prohibits direct transmission of Integral Image data. A number of highly efficient compression architectures are proposed today that outperform standard two-dimensional encoding schemes. However, critical issues regarding real-time compression for quality demanding applications are a primary concern to currently existing Integral Image encoders. In this work we propose a real-time FPGA-based encoder for Integral Image and integral video content transmission. The proposed encoder is based on a highly efficient compression algorithm used in Integral Imaging applications. Real-time performance is achieved by realizing a pipelined architecture, taking into account the specific structure of an Integral Image. The required memory access operations are minimized by adopting a systolic concept of data flow through the core processing elements, further increasing the performance boost. The encoder targets, real-time, broadcast-type high-resolution Integral Image and video sequences and performs three orders of magnitude faster than the analogous software approach.












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Acknowledgments
This work was realized under the framework 8.3 of the Reinforcement Programme of Human Research Manpower (“PENED 2003”-03ED656), cofunded 25% by the General Secretariat for Research and Technology, Greece, 75% by the European Social Fund and by the private sector.
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Chaikalis, D.P., Sgouros, N.P., Maroulis, D.E. et al. Real-time compression architecture for efficient coding in autostereoscopic displays. J Real-Time Image Proc 5, 45–56 (2010). https://doi.org/10.1007/s11554-009-0124-2
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DOI: https://doi.org/10.1007/s11554-009-0124-2