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Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec

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Abstract

The 3D discrete cosine transform and its inverse (3D DCT/IDCT) extend the spatial compression properties of conventional 2D DCT to the spatio-temporal coding of 2D videos. The 3D DCT/IDCT transform is particularly suited for embedded systems needing the low-complexity implementation of both video encoder and decoder, such as mobile terminals with video-communication capabilities. This paper addresses the problem of real-time and low-power 3D DCT/IDCT processing by presenting a context-aware fast transform algorithm and a family of VLSI architectures characterized by different levels of parallelism. Implemented in submicron CMOS technology, the proposed hardware macrocells support the real-time processing of main video formats (up to high definition ones with an input rate of tens of Mpixels/s) with different trade-offs between circuit complexity, power consumption and computational throughput. Voltage scaling and adaptive clock-gating strategies are applied to reduce the power consumption versus the state of the art.

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Notes

  1. It adds new features versus previous H.263 and MPEG2 schemes such as de-blocking filter, intraframe prediction, motion estimation with multiple reference frames and variable block sizes, CABAC entropy coding.

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Acknowledgments

The support of the VLSI systems research group-University of Pisa is gratefully acknowledged.

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  1. Department of Information Engineering, University of Pisa, via G. Carsuo 16, 56122, Pisa, Italy

    Sergio Saponara

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  1. Sergio Saponara
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Correspondence to Sergio Saponara.

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Saponara, S. Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec. J Real-Time Image Proc 7, 43–53 (2012). https://doi.org/10.1007/s11554-010-0174-5

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