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Real-time H.264/AVC baseline decoder implementation on TMS320C6416

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Abstract

The H.264/AVC Advanced Video Coding standard (AVC) is poised to enable a wide range of applications. However, its increased complexity creates a big challenge for efficient software implementations. This work develops and optimises the H.264/AVC video decoder level two on the TMS320C6416 Digital Signal Processor (DSP) for video conference applications. In order to accelerate the decoding speed, several algorithmic optimisations have been ported to inverse entropy decoding and intra-prediction modules. The parallelism between algorithm execution and data transfers was fully exploited using Enhanced Direct Memory Access (EDMA) engine. Furthermore, based on the DSP architectural features, various core-specific optimisation techniques were adopted leading to an increase in speed by up to 70%. Intensive experimental tests prove that a real-time decoding on TMS320C6416 DSP running at 720 MHz is obtained for Common Intermediate Format resolution (CIF 352 × 288).

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Acknowledgments

This work was conducted at ESIEE France and LETI Tunisia under cooperation number TMHESR96-2622-E-305. It was supported by a grant from Tunisian Ministry of higher education and scientific research.

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Authors and Affiliations

  1. University of Sfax, National School of Engineering, 3038, Sfax, Tunisia

    Imen Werda, Taheni Dammak & Nouri Masmoudi

  2. ESIEE—IGM LabInfo UMR 8049, Cité Descartes, Noisy le Grand, 93162, Paris, France

    Thierry Grandpierre

  3. University of Sfax, High Institute of Electronics and Communication, 3018, Sfax, Tunisia

    Mohamed Ali Ben Ayed

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  1. Imen Werda
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  2. Taheni Dammak
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  3. Thierry Grandpierre
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  4. Mohamed Ali Ben Ayed
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  5. Nouri Masmoudi
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Correspondence to Imen Werda.

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Werda, I., Dammak, T., Grandpierre, T. et al. Real-time H.264/AVC baseline decoder implementation on TMS320C6416. J Real-Time Image Proc 7, 215–232 (2012). https://doi.org/10.1007/s11554-010-0181-6

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  • DOI: https://doi.org/10.1007/s11554-010-0181-6

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