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Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

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Abstract

Highly regular multi-processor architectures are suitable for inherently highly parallelizable applications such as most of the image processing domain. Systems embedded in a single programmable chip platform (SoPC) allow hardware designers to tailor every aspect of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of cores, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on a SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirements and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs (Intellectual Property). We present both software and hardware implementation with performance results on a Xilinx SoPC target.

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References

  1. Derutin, J.P., et al.: Simd, smp and mimd-dm parallel approaches for real-time 2d image stabilization. In: CAMP 2005. Computer Architecture for Machine Perception, pp. 73–80 (2005)

  2. Taylor, M., et al.: Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ilp and streams. In: ISCA ’04. Proceedings of the 31st international symposium on computer architecture, Munchen, Germany, pp. 2–13 (2004)

  3. Guerrier, P., et al.: A generic architecture for on-chip packet-switched interconnections. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 250–256 (2000)

  4. Goossens, K., et al.: Networks on silicon: combining best-effort and guaranteed services. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 423–425 (2002)

  5. Goossens, K., et al.: A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification. In: Design, Automation and Test in Europe Conference and Exhibition, pp. 1182–1187 (2005)

  6. Evain, S., et al.: Microspider: a cad tool for efficient NoC design. In: Norchip Conference, pp. 218–221 (2004)

  7. Yu, Z., et al.: AsAP: An Asynchronous Array of Simple Processors. IEEE J. Solid State Circuits. vol. 43, no. 3, March 2008, pp. 695–705 (2008)

  8. Morimoto, C.: Electronic Digital Stabilization: Design and Evaluation, with Applications. PhD manuscript, University of Maryland (1997)

  9. Duric, Z., et al.: Shooting a smooth video with a shaky camera. Mach. Vis. Appl. 13, 303–313 (2003)

    Google Scholar 

  10. Zhu, Z., et al.: Camera stabilisation based on 2.5D motion estimation and inertial motion filtering. In: Int Conf Intell. Veh., pp. 329–334 (1998)

  11. Horn, B., et al.: Determining optical flow. Artif. Intell., 17, 185–204, Elsevier, Amsterdam (1981)

    Google Scholar 

  12. Barron, J., et al.: Performance of optical flow techniques. Int. J. Comput. Vis., 12(1), 43–77 (1994)

    Article  MathSciNet  Google Scholar 

  13. Verri, A., et al.: Motion field and optical flow: Qualitative properties. In: IEEE Trans. Pattern Anal. Mach. Intell., 11(8), 490–498 (1989)

  14. Harris, C., et al.: A combined corner and edge detector. In: 4th Alvey Vision Conference, pp. 147–151 (1988)

  15. Pourreza, H., et al.: Weighted multiple bit-plane matching, a simple and efficient matching criterion for electronic digital image stabilizer application. In: 6th International Conference on Signal Processing, vol. 2, pp. 957–960 (2002)

  16. Tsai, D., et al.: The evaluation of normalized cross correlations for defect detection. Pattern Recognit. Lett. 24, 2525–2535 (2003)

    Google Scholar 

  17. Viola, P., et al.: Rapid Object Detection using a Boosted Cascade of Simple Features. In: IEEE Conference on Computer Vision and Pattern Recognition, pp. 511–519 (2001)

  18. Hockney, R.W., Jessope, C.R.: Parallel Computers 2: Architecture, Programming and Algorithms, 2nd edn. pp. 350 ff and pp. 576 ff. Adam Hilger, Bristol (1988)

  19. AVNET, Xilinx Virtex-4 LX Evaluation Kit(ADS-XLX-V4LX-EVL25-G), Designed by AVNET. http://www.em.avnet.com

  20. Mateos, R., et al.: Hardware/software co-simulation environment for csoc with soft processors. In: IEEE International Conference on Field-Programmable Technology ICFPT’04, pp. 109–114 (2004)

  21. Craven, S., et al.: A methodology for generating application-specific heterogeneous processor arrays. In: HICSS ’06: 39th Annual Hawaii International Conference on System Sciences, pp. 251a–251a (2006)

  22. Leupers, R., Marwedel P.: Retargetable Code Generation based on Structural Processor Descriptions. In: Design Automation for Embedded Systems, vol. 3, pp. 1–36 (1998)

  23. Freericks, M.: The nML machine description formalism. Technical Report TR SM-IMP/DIST/08, TU Berlin CS Department (1993)

  24. Hadjiyiannis, G., Hanono, S., Devadas, S.: ISDL: An Instruction Set Description Language for Retargetability. In: Proceedings of the 34th Design Automation Conference (June 1997), pp. 299–302

  25. Morimoto, T., Saito, K., Nakamura, H., Boku, T., Nakazawa, K.: Advanced processor design using hardware description language AIDL. In: Design Automation Conference 1997. ASP-DAC ’97: Asia and South Pacific, pp. 387–390 (1997)

  26. Zivojnovic, V., Pees, S., Meyr, H.: LISA– machine description language and generic machine model for HW/SW co-design. In: Proceedings of the IEEE Workshop on VLSI Signal Processing, San Francisco, pp. 127–136 (1996)

  27. Halambi, A., et al.: EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), November 1999, pp. 485–490

  28. Gorjiara, B., Reshadi, M., Gajski, D.: Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific Pipelined IPs, on International Conference on Computer Design (ICCD), pp. 1–6 (2006)

  29. Processor Designer Datasheet. http://www.synopsys.com/Tools/SLD/ProcessorDev/Pages/default.aspx

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Authors and Affiliations

  1. LASMEA, UMR 6602 du CNRS, Université Blaise Pascal, Clermont-Ferrand, France

    Lionel Damez, Loic Sieler, Alexis Landrault & Jean Pierre Dérutin

Authors
  1. Lionel Damez
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  2. Loic Sieler
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  3. Alexis Landrault
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  4. Jean Pierre Dérutin
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Correspondence to Loic Sieler.

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Damez, L., Sieler, L., Landrault, A. et al. Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach. J Real-Time Image Proc 6, 47–58 (2011). https://doi.org/10.1007/s11554-010-0184-3

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  • DOI: https://doi.org/10.1007/s11554-010-0184-3

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