Skip to main content

Advertisement

SpringerLink
Log in

FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration

  • Special Issue
  • Published:
Journal of Real-Time Image Processing Aims and scope Submit manuscript

Abstract

This paper presents a combination of novel feature vectors construction approach for face recognition using discrete wavelet transform (DWT) and field programmable gate array (FPGA)-based intellectual property (IP) core implementation of transform block in face recognition systems. Initially, four experiments have been conducted including the DWT feature selection and filter choice, features optimisation by coefficient selections and feature threshold. To examine the most suitable method of feature extraction, different wavelet quadrant and scales have been evaluated, and it is followed with an evaluation of different wavelet filter choices and their impact on recognition accuracy. In this study, an approach for face recognition based on coefficient selection for DWT is presented, and the significant of DWT coefficient threshold selection is also analysed. For the hardware implementation, two architectures for two-dimensional (2-D) Haar wavelet transform (HWT) IP core with transpose-based computation and dynamic partial reconfiguration (DPR) have been synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. Experimental results and comparisons between different configurations using partial and non-partial reconfiguration processes and a detailed performance analysis of the area, power consumption and maximum frequency are also discussed in this paper.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. Amira, A., Farrell, P.: An automatic face recognition system based on wavelet transforms. In: IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005, vol. 6, 6252–6255 (2005)

  2. Nicholl, P., Ahmad, A., Amira, A.: A novel feature vectors construction approach for face recognition. In: Gavrilova, M., Tan, C., Moreno, E. (eds.) Transactions on Computational Science XI. Lecture Notes in Computer Science, vol. 6480, pp. 223–248. Springer, Berlin

  3. Zhao, W., Chellappa, R., Phillips, P.J., Rosenfeld, A.: Face recognition: a literature survey. ACM Comput. Surv. 35(4), 399–458 (2003)

    Article  Google Scholar 

  4. http://www.cognitec-systems.de. Accessed 10 Jan 2009 (online)

  5. http://www.l1id.com. Accessed 10 Jan 2009 (online)

  6. http://www.geometrix.com. Accessed 10 Jan 2009 (online)

  7. http://www.genextech.com. Accessed 10 Jan 2009 (online)

  8. http://www.animetrics.com. Accessed 10 Jan 2009 (online)

  9. Dang, P.: VLSI architecture for real-time image and video processing systems. J Real Time Image Process. 1, 57–62 (2006)

    Article  Google Scholar 

  10. Stokes, M.L.: A brief look at FPGAs, GPUs and cell processors. J. Int. Test Eval. Assoc. (ITEA), 9–11 (2007)

  11. Todman, T.J., Constantinides, G.A., Wilton, S.J.E., Mencer, O., Luk, W., Cheung, P.Y.K.: Reconfigurable computing: architectures and design methods. IEE Proc. Comp. Digital Tech. 152(2), 193–207 (2005)

    Article  Google Scholar 

  12. Rousseau, B., Manet, P., Galerin, D., Merkenbreack, D., Legat, J.-D., Dedeken, F., Gabriel, Y.: Enabling certification for dynamic partial reconfiguration using a minimal flow. In: Design, Automation Test in Europe Conference Exhibition, 2007. DATE ’07, pp. 1–6 (2007)

  13. Stollnitz, E.J., DeRose, T.D., Salesin, D.H.: Wavelets for computer graphics: a primer, part 1. IEEE Comput. Graph. Appl. 15(3), 76–84 (1995)

    Article  Google Scholar 

  14. Samaria, F., Harter, A.: Parameterization of a stochastic model for human face identification. In: IEEE Workshop on Applications of Computer Vision, Sarasota, FL (1994)

  15. Bajaj, C., Ihm, I., Park, S.: 3D RGB image compression for interactive applications. ACM Trans. Graph. 20(1), 10–38 (2001)

    Article  Google Scholar 

  16. Ahmad, A., Krill, B., Amira, A., Rabah, H.: Efficient architectures for 3D HWT using dynamic partial reconfiguration. J. Syst. Archit. 56(8), 305–316 (2010)

    Article  Google Scholar 

  17. Nefian, A., Hayes M.: Hidden Markov models for face recognition. In: ICASSP98, pp. 2721–2724 (1998)

  18. Kim, J., Choi, J., Yi, J., Turk, M.: Effective representation using ICA for face recognition robust to local distortion and partial occlusion. IEEE Trans. Pattern Anal. Mach. Intell. 27(12), 1977–1981 (2005)

    Article  Google Scholar 

  19. Wang, H.Y., Wu, X.J.: Weighted PCA space and its application in face recognition. In: Proceedings of 2005 international conference on machine learning and cybernetics, 2005, Washington, DC, USA, 2005, pp. 4522–4527. IEEE Computer Society, USA

  20. Ayinde, O., Yang, Y.H.: Face recognition approach based on rank correlation of Gabor-filtered images. Pattern Recognit. 35(6), 1275–1289 (2002)

    Article  MATH  Google Scholar 

  21. Samaria, F.: Face Recognition using Hidden Markov Models. PhD thesis, Cambridge University Engineering Department (1994)

  22. Xue, Y., Tong, C.S., Chen, W.S., Zhang, W.: A modified non-negative matrix factorization algorithm for face recognition. In: ICPR ’06: Proceedings of the 18th International Conference on Pattern Recognition, Washington, DC, USA, 2006, pp. 495–498. IEEE Computer Society, USA

  23. Lu, J., Tan, Y.P.: Enhanced face recognition using tensor neighborhood preserving discriminant projections. In: 15th IEEE International Conference on Image Processing, 2008. ICIP 2008, pp. 1916–1919 (2008)

  24. Ersi, E.F., Zelek, J.S.: Local feature matching for face recognition. In: CRV ’06: Proceedings of the 3rd Canadian Conference on Computer and Robot Vision (CRV ’06), Washington, DC, USA, 2006, p. 4. IEEE Computer Society, USA

  25. http://www.xilinx.com. Accessed 10 Jan 2008 (online)

  26. Lysaght, P., Blodget, B., Mason, J., Young, J., Bridgford, B.: Invited paper: enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration of Xilinx FPGAs. In: International Conference on Field Programmable Logic and Applications, 2006. FPL ’06, pp. 1–6. August 2006

  27. Parris, M.G.: Optimizing dynamic location realizations of partial reconfiguration of FGPAs. Master thesis, School of Electrical Engineering and Computer Science, University of Central Florida Orlando, 2009

  28. Huang, J., Parris, M., Lee, J., Demara, R.F.: Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration. ACM Trans. Embed. Comput. Syst. 9(1), 9–18 (2009)

    Article  Google Scholar 

  29. Krill, B., Ahmad, A., Amira, A., Rabah, H.: An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores. Signal Process. Image Commun. 25(5), 377–387 (2010)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Engineering, Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia (UTHM), Johor, Malaysia

    Afandi Ahmad

  2. Nanotechnology and Integrated Bio-Engineering Centre (NIBEC), Faculty of Computing and Engineering, University of Ulster (Jordanstown Campus), Ulster, Northern Ireland

    Abbes Amira & Benjamin Krill

  3. School of Electronic, Electrical Engineering and Computer Science, The Queens University, Belfast, Northern Ireland

    Paul Nicholl

  4. Department of Electrical Engineering, College of Engineering, Qatar University, Doha, Qatar

    Abbes Amira

Authors
  1. Afandi Ahmad
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Abbes Amira
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Paul Nicholl
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Benjamin Krill
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Abbes Amira.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Ahmad, A., Amira, A., Nicholl, P. et al. FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration. J Real-Time Image Proc 8, 327–340 (2013). https://doi.org/10.1007/s11554-011-0221-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11554-011-0221-x

Keywords

Search

Navigation