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Fast low-complexity computation and real-time architecture for H.264/AVC intra-prediction

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Abstract

This paper presents fast and low-complexity architecture to implement the computation of 16 × 16 luminance and 8 × 8 chrominance blocks for H.264 intra prediction. To conserve arithmetic operators and hasten processing speed, we propose an architecture based on recycled computation without the need for a multiplier. Center-based computation is used to generate the pixels in plane mode using two parallel cores and the architecture is implemented using four-parallel inputs and two-parallel outputs to achieve high-speed processing. The architecture is a configurable structure capable of computing the parameters and generating the predicted pixels in DC and plane mode within only 239 cycles in the processing of YUV blocks. The high-speed prediction for H.264 encoding meets the requirement for real-time HDTV.

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Acknowledgments

This work was supported by the National Science Council, Taiwan, under nsc 96-2221-E-327-006-MY3-3.

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Authors and Affiliations

  1. National Yunlin University of Science and Technology, Douliou, Taiwan

    Shih-Chang Hsia

  2. National Kaohsiung First University of Science and Technology, Kaohsiung, Taiwan

    Wei-Chih Hsu & Ying-Chao Chou

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  1. Shih-Chang Hsia
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  2. Wei-Chih Hsu
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  3. Ying-Chao Chou
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Correspondence to Shih-Chang Hsia.

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Hsia, SC., Hsu, WC. & Chou, YC. Fast low-complexity computation and real-time architecture for H.264/AVC intra-prediction. J Real-Time Image Proc 9, 589–595 (2014). https://doi.org/10.1007/s11554-012-0245-x

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  • DOI: https://doi.org/10.1007/s11554-012-0245-x

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