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Implementation of a cost-shared transform architecture for multiple video codecs

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Abstract

The paper presents a cost-shared architecture to compute multiple integer discrete cosine transform (Int-DCT) of four video codecs—AVS, H.264/AVC, VC-1 and HEVC (under development). Based on the symmetric structure of the matrices and the similarity in matrix operation, we develop a generalized “decompose and share” algorithm to compute both 4 × 4 and 8 × 8 Int-DCT. The algorithm is later applied to the video codecs. The hardware share approach ensures maximum circuit reuse during the computation. The architecture is designed with only adders and shifters to reduce the hardware cost significantly. The design is implemented on FPGA and later synthesized in CMOS 0.18 μm technology.

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Acknowledgments

The authors would like to acknowledge the Natural Science and Engineering Research Council of Canada (NSERC) for its support to this research work.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, Canada

    Muhammad Martuza & Khan A. Wahid

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  1. Muhammad Martuza
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  2. Khan A. Wahid
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Correspondence to Khan A. Wahid.

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Martuza, M., Wahid, K.A. Implementation of a cost-shared transform architecture for multiple video codecs. J Real-Time Image Proc 10, 151–162 (2015). https://doi.org/10.1007/s11554-012-0266-5

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  • DOI: https://doi.org/10.1007/s11554-012-0266-5

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