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An efficient hardware implementation of parallel EBCOT algorithm for JPEG 2000

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Abstract

With the augmentation in multimedia technology, demand for high-speed real-time image compression systems has also increased. JPEG 2000 still image compression standard is developed to accommodate such application requirements. Embedded block coding with optimal truncation (EBCOT) is an essential and computationally very demanding part of the compression process of JPEG 2000 image compression standard. Various applications, such as satellite imagery, medical imaging, digital cinema, and others, require high speed and performance EBCOT architecture. In JPEG 2000 standard, the context formation block of EBCOT tier-1 contains high complexity computation and also becomes the bottleneck in this system. In this paper, we propose a fast and efficient VLSI hardware architecture design of context formation for EBCOT tier-1. A high-speed parallel bit-plane coding (BPC) hardware architecture for the EBCOT module in JPEG 2000 is proposed and implemented. Experimental results show that our design outperforms well-known techniques with respect to the processing time. It can reach 70 % reduction when compared to bit plane sequential processing.

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Authors and Affiliations

  1. Electronics and Micro-Electronics Laboratory, Faculty of Sciences, Monastir University, Monastir, Tunisia

    Taoufik Saidani, Mohamed Atri & Rached Tourki

  2. Electrical and Computer Engineering Department, Sultan Qaboos University, Muscat, Oman

    Lazhar Khriji

Authors
  1. Taoufik Saidani
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  2. Mohamed Atri
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  3. Lazhar Khriji
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  4. Rached Tourki
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Correspondence to Taoufik Saidani.

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Saidani, T., Atri, M., Khriji, L. et al. An efficient hardware implementation of parallel EBCOT algorithm for JPEG 2000. J Real-Time Image Proc 11, 63–74 (2016). https://doi.org/10.1007/s11554-013-0322-9

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  • DOI: https://doi.org/10.1007/s11554-013-0322-9

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