Abstract
In this paper, a Nios II processor based hardware/software co-design architecture with high expandability and development flexibility is proposed. The architecture integrates a pipelined color space converter (CSC), hardware accelerator (HA), and a LCD touch module (LTM) HA, which facilitates a high-speed implementation of RGB to YCbCr color space conversion with a real-time image display. To avoid the inefficiency of CSC circuit architecture due to massive floating-point multiplication operations in the conversion formulae, a GA-based evolutionary technique is used to realize the fast multiplierless CSC hardware architecture. Meanwhile, a pipeline design method is further applied to enhance the maximum operating frequency in circuit design. As compared to the commonly used floating-point based CSC architecture, the pipelined CSC HA in this paper has excellent advantages of low-complexity and high speed. After the mechanism is integrated into a system-on-a-programmable-chip (SOPC), the maximum operating frequency reached 168.12 MHz. That is, in every 0.11 s, the color space conversion can process a 512 × 512 image. This excellent result is practical to the fast development of different kind of image/video processing systems.















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Acknowledgments
We would like to thank the anonymous reviewers for their valuable comments. This research was supported by the National Science Council of the Republic of China under Contract Nos. NSC 100-2221-E-130-019 and NSC 100-2622-E-032-004-CC3.
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Li, SA., Chen, CY. & Chen, CH. Design of a shift-and-add based hardware accelerator for color space conversion. J Real-Time Image Proc 10, 193–206 (2015). https://doi.org/10.1007/s11554-013-0324-7
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DOI: https://doi.org/10.1007/s11554-013-0324-7