Abstract
This paper deals with the design and the implementation of an image recognition system based on FPGA devices. It explores an n-tuple methodology using node ‘grouping’ and the possible advantages offered by this little-known technique. The paper is based on the implementation of this concept by an FPGA device. A novel approach to the organization of the neural networks data in the n-tuple memory is introduced. The system was tested on a real-world recognition task—the recognition of road signs. The test results are presented and discussed. It is concluded that the designed system may be a powerful part of more complex equipment for the solution of many recognition issues.
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Acknowledgments
This research has been supported by the European Regional Development Fund and the Ministry of Education, Youth and Sports of the Czech Republic under the Regional Innovation Centre for Electrical Engineering (RICE), Project No. CZ.1.05/2.1.00/03.0094. This research has been also supported by the Department of Applied Electronics and Telecommunications at the University of West Bohemia.
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Burian, P., Holota, R. Fast image recognition based on n-tuple neural networks implemented in an FPGA. J Real-Time Image Proc 11, 155–166 (2016). https://doi.org/10.1007/s11554-013-0331-8
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DOI: https://doi.org/10.1007/s11554-013-0331-8