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High performance architecture for real-time HDTV broadcasting

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Abstract

A novel full search motion estimation co-processor architecture design is presented in this paper. The proposed architecture efficiently reuses search area data to minimize memory I/O while fully utilizing the hardware resources. A smart processing element (PE) and an efficient simple internal memory are the main components of the proposed co-processor. An efficient algorithm is used for loading both the current block and the search area inside the PE array. The search area data flow horizontally while the current block data are stationary. As a result, the speed of the co-processor is improved in terms of the throughput and the operating frequency compared to the state-of-the-art techniques. A smart local memory and PE design guarantees a simple and a regular data flow. The design of the local memory is implemented using only registers and a simple counter. This simplifies the design by avoiding the use of complicated addressing to write or read into/from the local memory. The proposed architecture is implemented using both the FPGA and the ASIC flow design tools. For a search range of 32 × 32 and block size of 16 × 16, the architecture can perform motion estimation for 30 fps of HDTV video at 350 MHz and easily outperforms many fast full search architectures.

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Acknowledgments

The authors acknowledge the support of the Deanship of Scientific Research—University of Bahrain—Bahrain for their financial support to finalize this work.

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Authors and Affiliations

  1. University of Bahrain, Sakhair, Bahrain

    Yasser Ismail, Wael El-Medany & Hessa Al-Junaid

  2. Central Michigan University, Mt Pleasant, USA

    Ahmed Abdelgawad

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  1. Yasser Ismail
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  2. Wael El-Medany
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  3. Hessa Al-Junaid
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  4. Ahmed Abdelgawad
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Correspondence to Yasser Ismail.

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Ismail, Y., El-Medany, W., Al-Junaid, H. et al. High performance architecture for real-time HDTV broadcasting. J Real-Time Image Proc 11, 633–644 (2016). https://doi.org/10.1007/s11554-014-0430-1

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