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Analog signal processing solution for machine vision applications

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Abstract

The field of machine vision is continuously evolving. There are new products coming into the market that have very severe size, weight and power constraints and handle very high computational loads simultaneously. Existing architectures and digital image processing solutions will not be able to meet these ever-increasing demands. There is a need to develop novel architectures and image processing solutions to address these requirements. The major contribution of this work is to show that analog signal processing is a solution to this problem. The analog processor will be used as an augmentation device which works in parallel with the digital processor, making the system faster and more efficient. We have developed a prototype of an analog processing board using commercially available off-the-shelf components and demonstrated that a prototype development has several advantages over a direct integrated circuit design. We focus on providing experimental results that demonstrate functionality of the analog processing board and show that the performance of the prototype board for low-level and mid-level image processing tasks is equivalent to a digital implementation. To demonstrate improvement in speed and power consumption over other systems, we propose an integrated circuit design of the analog processor and show that such an analog processor would be 100× faster than existing FPGAs and 5× faster than state-of-the-art GPUs. We also compare the performance of the proposed integrated circuit design against other analog processors reported in the literature. We report a case study in which we use the processor for an object detection and recognition application and show that the processor has excellent performance.

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References

  1. Alma Delic, A., et al.: Programmable state-variable filter with wide frequency and Q tuning range. Int. J. Electron. Electr. Eng. 3(3), 207–211 (2015)

    Google Scholar 

  2. Analog Devices: ADG601/602 SPST switches. ADG601/602 datasheet

  3. Analog Devices: AD8336 wide bandwidth, DC-coupled VGA. AD8336 datasheet

  4. Analog Devices: AD4817-1 low-noise, 1 GHz, FastFET Op Amps. AD4817 datasheet

  5. Analog Devices: ADL5391 DC to 2 GHz, multiplier. ADL5391 datasheet

  6. Botella, G., et al.: Bio-inspired robust optical flow processor system for VLSI implementation. Electron. Lett. 45(25), 1304–1305 (2009)

    Article  Google Scholar 

  7. Botella, G., et al.: Robust bioinspired architecture for optical-flow computation. IEEE Trans. VLSI Syst. 18(4), 616–629 (2010)

    Article  MathSciNet  Google Scholar 

  8. Carmona, R., et al.: A 0.5 µm CMOS CNN analog random access memory chip for massive image processing. In: IEEE International workshop on CNN and their Applications (1998)

  9. Christopher Soell., et al.: A CMOS image sensor with analog pre-processing capability suitable for smart camera applications. In: IEEE ISPACS, pp. 279–284 (2015)

  10. Corradi, F., et al.: Decision making and perceptual bistability in spike-based neuromorphic VLSI systems. In: IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, pp. 2708–2711 (2015)

  11. Culurciello, E.: Enabling machines to perceive the world. Teradeep Inc. (2014)

  12. De Simone, F., et al.: A comparative study of color image compression standards using perceptually driven quality metrics. SPIE, Optical Engineering Applications (2008)

  13. Devereux, V.G.: Limiting of YUV digital video signals. BBC Research Department (1987)

  14. Dosselmann, R., Yang, X.D.: A comprehensive assessment of the structural similarity index. SIViP 5(1), 81–91 (2009)

    Article  Google Scholar 

  15. Dudek, P., et al.: A general-purpose processor-per-pixel analog SIMD vision chip. IEEE Trans. Circuits Syst. 52(1), 13–20 (2005)

    Article  Google Scholar 

  16. Espejo, S., et al.: A 0.8 µm CMOS programmable analog-array-processing vision chip with local logic and image-memory. In: European IEEE Solid-State Circuits Conference, pp. 280–283 (1996)

  17. Gonzalez, R., Woods, R.: Digital Image Processing. Prentice Hall, Upper Saddle River (2002)

    Google Scholar 

  18. Gotarredona, R., et al.: A neuromorphic cortical-layer microchip for spike-based event processing vision systems. IEEE Trans. Circuits Syst. I Regul. Pap. 53(12), 2548–2566 (2006)

    Article  Google Scholar 

  19. Hall, T.: Field-programmable analog arrays: a floating-gate approach. Ph.D. Dissertation, Georgia Institute of Technology, Atlanta, GA (2004)

  20. Harpe, P., et al.: A 7-to-10 bit 0-to-4 MS/s flexible SAR ADC with 6.5-to-16fJ/conversion step. In: IEEE J. Solid-State Circuits, pp. 472–474 (2012)

  21. Indiveri, G., et al.: A reconfigurable neuromorphic VLSI multi-chip system applied to visual motion computation. In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, (MicroNeuro ‘99), Granada, pp. 37–44 (1999)

  22. Jendernalik, W., et al.: Analog CMOS processor for early vision processing with highly reduced power consumption. In: 20th European Conference on Circuit Theory and Design, pp. 745–748 (2011)

  23. Jendernalik, W., et al.: CMOS realization of analogue processor for early vision processing. Bull. Pol. Acad. Sci.: Tech. Sci. 59(2), 141–147 (2011)

    Google Scholar 

  24. Kim, J.-H., et al.: A low power analog CMOS vision chip for edge detection using electronic switches. ETRI J. 27(5), 539–544 (2005)

    Article  Google Scholar 

  25. Kinget, P., et al.: A programmable analog cellular neural network CMOS chip for high speed image processing. IEEE J. Solid-State Circuits 30(3), 235–243 (1995)

    Article  Google Scholar 

  26. Klein, J.-O., et al.: Low power image processing: analog versus digital comparison. In: IEEE International Workshop on Computer Architecture for Machine Perception, pp. 111–115 (2005)

  27. Kong, J. S., et. al.: A 160x120 edge detection vision chip for neuromorphic systems using logarithmic active pixel sensor with low power dissipation. In: ICONIP, pp. 97–106 (2007)

  28. Krizhevsky, A., et al.: ImageNet classification with deep convolutional neural networks. In: Advances in Neural Information Processing Systems, pp. 1097–1105 (2012)

  29. Lin, W.-T., et al.: A 12-bit 40 nm DAC achieving SFDR >70 dB at 1.6 GSPS and IMD <−61 dB at 2.8 GSPS with DEMDRZ technique. In: IEEE Journal of Solid-State Circuits, pp. 708–717 (2014)

    Article  Google Scholar 

  30. Linan, G., et al.: A 0.5 µm CMOS 106 transistors analog programmable array processor for real-time image processing. In: IEEE Solid-State Circuits Conference, pp 358–361 (1999)

  31. Liu, S.-C.: A neuromorphic aVLSI model of global motion processing in the fly. IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process 47(12), 1458–1467 (2000). doi:10.1109/82.899640

    Article  Google Scholar 

  32. Miao, W., et al.: A programmable SIMD vision chip for real-time vision applications. IEEE J. Solid-State Circuits 43(6), 1470–1479 (2008). doi:10.1109/JSSC.2008.923621

    Article  Google Scholar 

  33. Minicircuit: RLP-70+ low pass filter. RLP-70+ datasheet

  34. Movidius: Software programmable media processor (2011)

  35. Movidius: Myriad 2 MA2×5× vision processor VPU product brief

  36. Nvidia: NVIDIA Tesla P100. In: Nvidia whitepaper

  37. Nvidia: GPU-based deep learning inference: a performance and power analysis. In: Nvidia whitepaper

  38. Ovtcharov, K., et al.: Accelerating deep convolutional neural networks using specialized hardware. In: Microsoft Research (2015)

  39. Pan, X., Graeb, H.: Reliability optimization of analog integrated circuits considering the tradeoff between lifetime and area. ICMAT, Elsevier 52(8), 1559–1564 (2011)

    Google Scholar 

  40. Papananos, Y.: Feasibility of analogue computation for image processing application. IEEE Proc.- Circuits, Devices Sys. 136(1), 9–13 (1989)

    Article  Google Scholar 

  41. Parvizi, M., et al.: An ultra-low-power wideband inductorless CMOS LNA with tunable active shunt-feedback. In: IEEE Trans. Microw. Theory Tech. 64(6) (2016)

    Article  Google Scholar 

  42. Potluri, S., et al.: CNN based high performance computing for real-time image processing on GPU. In: IEEE Proceedings of the Joint INDS and ISTET, pp. 1–7 (2011)

  43. Schlottmann, C., et al.: Vector matrix multiplier on field programmable analog array. In: IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 1522–1525 (2010)

  44. Shameli, A. et al.: A Novel ultra-low power low noise amplifier using differential inductor feedback. In: IEEE European Solid-State Conference, pp. 352–355 (2006)

  45. Sharad, M., et al.: Ultra-low energy analog image processing using spin based neurons. In: IEEE/ACM International Symposium on Nanoscale Architectures, pp. 211–217 (2012)

  46. Shimonomura, K., et al.: Neuromorphic binocular vision system for real-time disparity estimation. In: IEEE International Conference on Robotics and Automation, pp. 4867–4872, Roma (2007)

  47. Stocker, A.: Analog VLSI focal-plane array with dynamic connections for the estimation of piecewise-smooth optical flow. IEEE Trans. Circuits Syst. I Regul. Pap. 51(5), 963–973 (2004)

    Article  Google Scholar 

  48. Tang, H.: Study of design for reliability of RF and analog integrated circuits. Ph.D. Dissertation, University of Central Florida, Orlando, Florida (2012)

  49. Texas Instruments: LMH6552 1.5 GHz fully differential amplifier. LMH6552 Datasheet, April 2007 (revised Jan 2015)

  50. Valle, M. et al.: An analog VLSI neural network for real-time image processing in industrial applications. In: Seventh IEEE ASIC conference, pp. 37–40 (1994)

  51. Vornicu, I., et al.: Image processing using a CMOS analog parallel architecture. In: IEEE Proceedings on CAS, vol. 2 (2010)

  52. Winkler, S.: Digital Video Quality: Vision Models and Metrics. Wiley, West Sussex (2005)

    Book  Google Scholar 

  53. Wyatt, J.L., et al.: The MIT Vision chip project: analog VLSI systems for fast image acquisition and early vision processing. In: IEEE International Conference on Robotics and Automation (1991)

  54. Xilinx: 7 Series FPGAs overview. DS180 (v2.0) (2016)

  55. Xilinx: Artix-7 FPGAs data sheet: DC and AC switching characteristics. Artix-7 datasheet (2015)

  56. Xinyu, W., et al.: Homogeneous spiking neuromorphic system for real-world pattern recognition. IEEE J. Emerg. Sel.Top. Circuits Syst. 5(2), 254–266 (2015)

    Article  Google Scholar 

  57. Yagi, T., Shimonomura, K.: Silicon primary visual cortex designed with a mixed analog-digital architecture. In: International Joint Conference on Neural Networks, pp. 2723–2728, Orlando, FL (2007)

  58. Yin, C., et al., “A 0.5 V 34.4uW 14.28kfps 105 dB smart image sensor with array level analog signal processing”, IEEE Solid-State Circuits Conference, pp. 97-100, Nov. 2013

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, USA

    Nihar Athreyas & Dev Gupta

  2. Spero Devices Inc., 43 Nagog Park, Acton, MA, USA

    Jai Gupta

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  1. Nihar Athreyas
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  2. Dev Gupta
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Correspondence to Nihar Athreyas.

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Athreyas, N., Gupta, D. & Gupta, J. Analog signal processing solution for machine vision applications. J Real-Time Image Proc 16, 1607–1628 (2019). https://doi.org/10.1007/s11554-017-0669-4

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  • DOI: https://doi.org/10.1007/s11554-017-0669-4

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