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High-throughput parallel DWT hardware architecture implemented on an FPGA-based platform

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Abstract

To detect fast myoclonus jerks, doctors require a full-HD video capture of the patient at 100 frames per second. Real-time video compression becomes mandatory to archive/transmit the generated data. To achieve this goal, we used a certified medical imaging coder based on discrete wavelet transform (DWT). Thus, a major challenge was to design a 2D DWT architecture, achieving the throughput of 100 full-HD frames/s. The novel unified 2D DWT computation architecture performs both horizontal and vertical transform simultaneously and eliminates the problem of column-wise image pixel accesses to/from the off-chip DDR RAM. All of these factors have led to the reduction of the required off-chip DDR RAM bandwidth by more than 2X. The proposed concept uses four-port line buffers leading to pipelined parallel processing of direct memory access (DMA) read, horizontal 1D DWT, vertical 1D DWT, and DMA write. The proposed architecture has cycles per pixel of just 1/8, making it far exceeds 100 full-HD fps and well positioned for the 4K and 8K video processing. Finally, we highlighted that the developed architecture is highly scalable, outperforms state of the art and is deployed in a first video EEG medical prototype.

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Acknowledgements

This paper is based upon the work in the Smart EEG project. This project is conducted jointly with the companies CIRA, Partelec, ACACIA, 2CSI, the hospitals Georges Pompidou and Lariboisiere, ETIS and LIP6 labs. The authors thank all the project members for their constructive debate.

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Authors and Affiliations

  1. Laboratoire d’Informatique de Paris 6, UMR 7606, UPMC Univ Paris 6, Paris, France

    Mohammed Shaaban Ibraheem, Khalil Hachicha, Syed Zahid Ahmed, Laurent Lambert & Patrick Garda

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  1. Mohammed Shaaban Ibraheem
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  2. Khalil Hachicha
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  3. Syed Zahid Ahmed
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  4. Laurent Lambert
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Correspondence to Khalil Hachicha.

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Ibraheem, M.S., Hachicha, K., Ahmed, S.Z. et al. High-throughput parallel DWT hardware architecture implemented on an FPGA-based platform. J Real-Time Image Proc 16, 2043–2057 (2019). https://doi.org/10.1007/s11554-017-0711-6

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  • DOI: https://doi.org/10.1007/s11554-017-0711-6

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