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Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders

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Abstract

This work proposes several intrinsics on a reconfigurable processor intended for HEVC decoding and software pipelining algorithms with a coarse-grained array (CGA) architecture as well as the proposed intrinsic instructions. Software pipelining algorithms are developed for the CGA acceleration of inverse transform, pixel reconstruction, de-blocking filter and sample adaptive offset modules. To enable efficient software pipelining, several very-long instruction-word-based intrinsics are designed in order to maximize the parallelization rather than the computational acceleration. We found that the HEVC decoder with the proposed intrinsics yields 2.3 times faster in running clock cycle than a decoder that does not use the intrinsics. In addition, the HEVC decoder with CGA pipelining algorithms executes 10.9 times faster than that without the CGA mode.

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Acknowledgements

This research was partly supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (NRF-2014R1A2A1A11052210) and the Ministry of Science, ICT and Future Planning (MSIP), Korea, under the Information Technology Research Center (ITRC) support program (IITP-2017-2016-0-00288) supervised by the Institute for Information & Communications Technology Promotion (IITP).

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Authors and Affiliations

  1. Department of Computer Engineering, Kwangwoon University, 20, Gwangun-ro, Nowon-gu, Seoul, Korea

    Yong-Jo Ahn, Jonghun Yoo, Hyun-Ho Jo & Donggyu Sim

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  1. Yong-Jo Ahn
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  2. Jonghun Yoo
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  3. Hyun-Ho Jo
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Correspondence to Donggyu Sim.

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Ahn, YJ., Yoo, J., Jo, HH. et al. Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders. J Real-Time Image Proc 16, 2173–2187 (2019). https://doi.org/10.1007/s11554-017-0729-9

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