Abstract
This paper presents a real time hardware implementation of the scale invariant feature transform (SIFT) algorithm. To achieve real time requirements, pipeline structures have been widely exploited both in the keypoint extraction and in the descriptor generation stages. Simplifications to the original algorithm have been also applied to allow a simpler hardware implementation. The proposed architecture has been synthesized on a Xilinx Virtex 5 FPGA. It generates 3072 descriptor vectors for VGA images at 99 frames per second at a clock rate of 100 MHz.
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Acknowledgements
This work has been partially funded by Spanish government project TEC2015‐66878‐C3‐2‐R (MINECO/FEDER, UE).
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Doménech-Asensi, G., Zapata-Pérez, J., Ruiz-Merino, R. et al. All-hardware SIFT implementation for real-time VGA images feature extraction. J Real-Time Image Proc 17, 371–382 (2020). https://doi.org/10.1007/s11554-018-0781-0
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DOI: https://doi.org/10.1007/s11554-018-0781-0