Skip to main content
SpringerLink
Log in

High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator

  • Special Issue Paper
  • Published:
Journal of Real-Time Image Processing Aims and scope Submit manuscript

Abstract

Real-time operation and low-power dissipation in video coding systems have become important research challenges, especially in mobile devices with limited battery and computational resources. Given the variety of applications able to manipulate videos and the growing number of video coding standards, current devices are expected to provide native support to multiple coding standards. Although state-of-the-art coding requires a wide set of tools focusing on coding efficiency, major tools are usually present in different standards with limited differences. Therefore, implementing dedicated architectures for each standard tool is an inefficient approach at both development time and silicon area. Fractional Motion Estimation (FME) and Motion Compensation (MC) are among the most computation-intensive tasks within video codecs and are used in all major video coding standards. Thus, this paper presents a multi-standard sample interpolator hardware design for the MC and FME with full support to MPEG-2, MPEG-4, H.264/AVC, HEVC, AVS, and AVS2. The proposed design is capable of UHD 8K (Ultra High Definition − 4320p@60fps) real-time interpolation when synthesized using a 45 nm standard-cell library. The circuit footprint occupies 65,508 µm2 and the power dissipation ranges from 14.58 to 65.316 mW for MPEG-2 and AVS2 operation modes, respectively.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

References

  1. Statista Inc: Mobile Internet: Statistics and facts on mobile internet usage. https://www.statista.com/statistics/271405/global-mobile-data-traffic-forecast/ (2017). Accessed 31 Aug 2017

  2. CISCO: Cisco Visual Networking index: Forecast and methodology, 2016–2021 white paper. http://www.cisco.com/c/en/us/solutions/collateral/service-provider/ip-ngn-ip-next-generation-network/white_paper_c11-481360.html (2017). Accessed 31 Aug 2017

  3. YOUTUBE: Youtube statistics. https://www.youtube.com/yt/press/pt-BR/statistics.html (2017). Accessed 31 Aug 2017

  4. ITU-T Recommendations: ITU-T H.265. [Online]. http://handle.itu.int/11.1002/1000/12455 (2016). Accessed 31 Aug 2017

  5. Sze, V., Budagavi, M., Sullivan, G.: High Efficiency Video Coding (HEVC)—Algorithms and Architectures. Springer, New York (2014)

    Book  Google Scholar 

  6. ISO/IEC-JCT1/SC29/WG11: High Efficiency Video Coding (HEVC) text specification draft 10, doc. JCTVC-L1003. Geneva, Switzerland (2013)

    Google Scholar 

  7. ITU-T Recommendations: ITU-T H.264. [Online]. https://www.itu.int/rec/T-REC-H.264 (2003). Accessed 31 Aug 2017

  8. Sullivan, G., Marpe, D., Wiegand, T.: The H.264/MPEG4 advanced video coding standard and its applications. IEEE Commun. Mag. 44, 134–143 (2006)

    Google Scholar 

  9. Grois, D., et al.: Performance comparison of H.265/MPEG-HEVC, VP9, and H.264/MPEG-AVC encoders. In: Picture Coding Symposium (PCS), pp. 394–397. San Jose, CA (2013)

  10. Mengzhe, L., Xiuhua, J., Xiaohua, L.: Analysis of H.265/HEVC, H.264 and VP9 coding efficiency based on video content complexity. In: IEEE International Conference on Computer and Communications (ICCC), pp. 420–424. Chengdu (2015)

  11. Lee, G., Yang, W., Wu, M., Lin, H.: Reconfigurable architecture design of motion compensation for multi-standard video coding. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2003–2006. Paris (2010)

  12. Gao, W., Ma, S.: Advanced Video Coding Systems. Springer, New York (2014)

    Book  Google Scholar 

  13. Workgroup, A.V.S.: Final draft of information technology—advanced coding of audio and video—part 2: video, in AVS workgroup Doc. N1214. Shanghai, China (2005)

    Google Scholar 

  14. Zatt, B., et al.: 3D Video Coding for Embedded Devices—Energy Efficient Algorithms and Architectures. Springer Science, New York (2013)

    Book  Google Scholar 

  15. QUALCOMM INC: Snapdragon 835 Processor. https://www.qualcomm.com/products/snapdragon/processors/835 (2017). Accessed 16 July 2017

  16. SAMSUNG ELECTRONICS CO. LTDA: Application Processor—Exynos 7 Octa (7420): http://www.samsung.com/semiconductor/products/exynos-solution/application-processor/EXYNOS-7-OCTA-7420 (2017). Accessed 16 July 2017

  17. APPLE INC: iPhone 7 specs. http://www.apple.com/iphone-7/specs/> (2017). Accessed 16 July 2017

  18. Henkel, J., Khdr, H., Pagani, S., Shafique, M.: New trends in dark silicon. In: 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–6. San Francisco, CA (2015)

  19. Li, H., Zhang, Y., Chao, H.: An optimally scalable and cost-effective fractional-pixel motion estimation algorithm for HEVC. In: IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 1399–1403. Vancouver, BC (2013)

  20. Chen, T., Huang, Y., Chen, L.: Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC. In: IEEE international conference on aoustics, speech, and signal processing, Montreal, Que., vol. 5, pp. 9–12 (2004)

  21. Diniz, C., Shafique, M., Bampi, S., Henkel, J.: A reconfigurable hardware architecture for fractional pixel interpolation in high efficiency video coding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2), 238–251 (2015)

    Article  Google Scholar 

  22. Li, E., Chen, Y.: Implementation of H.264 encoder on general-purpose processors with hyper-threading technology. In: Proceedings of SPIE, vol. 5308, Visual communications and image processing, Jose, California, pp. 384–395 (2004)

  23. Pastuszak, G., Jakubowski, M.: Optimization of the adaptive computationally-scalable motion estimation and compensation for the hardware H.264/AVC encoder. J. Signal Process. Syst. 82(3), 391–402 (2016)

    Article  Google Scholar 

  24. Pastuszak, G., Trochimiuk, M.: Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder. J. Real-Time Image Proc. 12(2), 517–529 (2016)

    Article  Google Scholar 

  25. Lung, C., Shen, C.: Design and implementation of a highly efficient fractional motion estimation for the HEVC encoder. J. Real-Time Image Process (2016). https://doi.org/10.1007/s11554-016-0663-2

    Google Scholar 

  26. Pastuszak, G., Trochimiuk, M.: Algorithm and architecture design of the motion estimation for the H.265/HEVC 4K-UHD encoder. J. Real-Time Image Proc. 11(4), 663–673 (2016)

    Article  Google Scholar 

  27. Wang, S., Zhou, D., Zhou, J., Yoshimura, T., Goto, S.: VLSI implementation of HEVC motion compensation with distance biased direct cache mapping for 8K UHDTV applications. IEEE Trans. Circuits Syst. Video Technol. 27(2), 380–393 (2017)

    Article  Google Scholar 

  28. León, J., Cárdenas, C., Castillo, E.: A High Parallel HEVC Fractional Motion Estimation architecture, pp. 1–4. IEEE ANDESCON, Arequipa (2016)

    Google Scholar 

  29. Aiyar, M., Kenchappa, R.: A high-performance and high-precision sub-pixel motion estimator-interpolator for real-time HDTV(8K) in MPEGH/HEVC coding. In: IEEE International Conference on Emerging Trends in Engineering, Technology and Science (ICETETS), pp. 1–8. Pudukkottai (2016)

  30. León, J., Cárdenas, C., Castillo, E.: A highly parallel 4K real-time HEVC fractional motion estimation architecture for FPGA implementation. In: IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 708–711. Monte Carlo (2016)

  31. Lee, G., Tai, T., Yang, W., Chen, C., Huang, C.: Reconfigurable interpolation architecture for multistandard video decoding. J. Signal Process. Syst. 84(2), 251–264 (2016)

    Article  Google Scholar 

  32. Zhou, D., Liu, P.: A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264. In: IEEE international symposium on circuits and systems (ISCAS), New Orleans, LA, pp. 2910–2913 (2007). https://doi.org/10.1109/ISCAS.2007.377858

  33. Zheng, J., Gao, W., Wu, D., Xie, D.: A novel VLSI architecture of motion compensation for multiple standards. IEEE Trans. Consum. Electron. 54(2), 687–694 (2008)

    Article  Google Scholar 

  34. Chen, X.: et. al.: A high performance and low bandwidth multi-standard motion compensation design for HD video decoder. IEICE Trans. Electr. E93-C(3), 253–260 (2010)

    Article  Google Scholar 

  35. Maich, H., et al.: A multi-standard interpolation filter for motion compensated prediction on high definition videos. In: IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), pp. 1–4. Montevideo (2015)

  36. Lu, L., McCanny, J., Sezer, S.: Subpixel interpolation architecture for multistandard video motion estimation. IEEE Trans. Circuits Syst. Video Technol. 19(12), 1897–1901 (2009)

    Article  Google Scholar 

  37. Paim, G.: High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards. In: IEEE International Conference on Image Processing (ICIP), pp. 2162–2166. Phoenix, AZ (2016)

  38. Penny, W., et al.: Real-time architecture for HEVC motion compensation sample interpolator for UHD videos. In: 28th Symposium on Integrated Circuits and Systems Design (SBCCI), pp. 1–6. Salvador (2015)

  39. Bossen, F.: Common test conditions and software reference configurations. Geneva (2013)

  40. Wang, T., et al.: A hardware efficient implementation of chroma interpolator for H.264 encoders. In: IEEE International Conference of Electron Devices and Solid-State Circuits, pp. 1–2. Tianjin (2011)

  41. NANGATE: Nangate Free PDK45 Open Cell Library. http://www.nangate.com/?page_id=2325 (2018). Accessed 3 July 2018

  42. CADENCE: Encounter RTL Compiler. http://www.cadence.com (2018). Accessed 3 July 2018

  43. McCann, K., et. al.: HM13—High Efficiency Video Coding Test Model (HM13) Encoder Discription, JCTVC-O1002. Geneva, Switzerland (2013)

    Google Scholar 

  44. AVS2 working group: Working draft 3 of advanced media coding Part 2—Video, document AVS2-N1955 of AVS2. Luoyang, China (2013)

    Google Scholar 

  45. ISO/IEC JTC1/SC29/WG11 and ITU-T SG16 Q.6: JM Reference SoftwareManual, doc. JVT-AE010. [Online]. http://iphome.hhi.de/suehring/ (2009). Accessed 31 Aug 2017

    Google Scholar 

Download references

Acknowledgements

We have a special acknowledgement to the National Council for Scientific and Technological Development (CNPq), Coordination of Improvement of Superior Education Staff (CAPES), and Research Support Foundation of Rio Grande do Sul (FAPERGS) by support this work.

Author information

Authors and Affiliations

  1. Video Technology Research Group, Group of Architectures and Integrated Circuits, Federal University of Pelotas (UFPel), Pelotas, RS, 96010-900, Brazil

    Wagner Penny, Jones Goebel, Guilherme Paim, Marcelo Porto, Luciano Agostini & Bruno Zatt

Authors
  1. Wagner Penny
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jones Goebel
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Guilherme Paim
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Marcelo Porto
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Luciano Agostini
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Bruno Zatt
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Wagner Penny.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Penny, W., Goebel, J., Paim, G. et al. High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator. J Real-Time Image Proc 16, 175–192 (2019). https://doi.org/10.1007/s11554-018-0832-6

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11554-018-0832-6

Keywords

Search

Navigation