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FPGA-based low-complexity high-throughput real-time hardware accelerator for robust watermarking

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Abstract

This paper presents an FPGA-based hardware accelerator for robust watermarking. By applying some novel transformation techniques, the DCT/IDCT algorithm is simplified in a hardware-friendly way by replacing the original complex multiplication/division and nonlinear function (cosine function) with addition and shift operations. Moreover, the architecture of this real-time accelerator is proposed with pipeline technique to improve throughput and hardware efficiency. The entire design is implemented on FPGA, which achieves up to 3.2 GBps (Giga Bytes per second) throughput. Finally, the experimental results show that the proposed accelerator has good performance.

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Authors and Affiliations

  1. School of Electrical Science and Engineering, Nanjing University, Nanjing, China

    Hangqi Ge & Jin Sha

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  1. Hangqi Ge
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  2. Jin Sha
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Correspondence to Hangqi Ge.

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Ge, H., Sha, J. FPGA-based low-complexity high-throughput real-time hardware accelerator for robust watermarking. J Real-Time Image Proc 16, 813–820 (2019). https://doi.org/10.1007/s11554-019-00882-x

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  • DOI: https://doi.org/10.1007/s11554-019-00882-x

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