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Quality-power configurable flexible coding order hardware design for real-time 3D-HEVC intra-frame prediction

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Abstract

The emerging of 3D video-capable embedded mobile devices is expected due to the popularization of multimedia services and the demand for novel immersive video technologies. Such devices require efficient hardware-friendly heuristics to deal with strict processing requirements and limited energy supply. To contribute to these requirements, this work presents a complete 3D-HEVC intra-frame prediction hardware design that supports a flexible coding order between texture and depth channels. The developed hardware employs hardware-friendly constraints and novel heuristics to explore inter-channel redundancies and to reduce the computational effort through the novel inter-channel directional structure detector heuristic. The designed 3D-HEVC intra-frame prediction system dissipates 384.6 mW while processing three HD 1080p views (texture + depth) at 30 frames per second in real-time. To the best of our knowledge, this is the first work to propose a complete 3D-HEVC intra-frame prediction system with support to flexible coding order. In addition, this is the only hardware design to process luminance and chrominance texture channels and depth channel.

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Funding

This research was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior—Brasil (CAPES)—Finance Code 001. It was also financed in part by the Fundação de Amparo à Pesquisa do Estado do Rio Grande do Sul—Brasil (FAPERGS), and by the Conselho Nacional de Desenvolvimento Científico e Tecnológico—Brasil (CNPq).

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Correspondence to Murilo R. Perleberg.

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Perleberg, M.R., Afonso, V., Borges, V.A. et al. Quality-power configurable flexible coding order hardware design for real-time 3D-HEVC intra-frame prediction. J Real-Time Image Proc 19, 969–984 (2022). https://doi.org/10.1007/s11554-022-01238-8

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