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VLSI architecture and implementation of HDR camera signal processor

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Abstract

The camera imaging built with high dynamic range (HDR) techniques can effectively improve the quality of images and so increase the recognition rate for computer vision systems. This paper presents the parallel architecture with a pipelined schedule to realize a real-time HDR processor based on a high-performance algorithm. With the hardware-oriented design, the processing kernel employs a near approach to reduce the computational circuit. The full HDR chip is realized with the module-by-module design and simulation. The main modules include the inverse module, the dark enhancement circuit, the parameter statistics circuit, the picture type judgment circuit, the mixing circuit and the bright enhancement circuit. Finally, these modules are combined with the pipelined schedule to realize a high-speed HDR core. In total, the latency time of the circuit is 4 line-buffer length added 14 clocks. This circuit is mapping to one FPGA (Field Programmable Gate Array) chip to verify its performance. The results demonstrate that the operation frequency can achieve to near 120 MHz, and data throughput rate is 360 M bytes per second. This chip can output one RGB (Red, Green, Blue) pixel per cycle, which can meet the requirement of high-resolution HDR camera performance.

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Funding

Ministry of Science and Technology, Taiwan (Grant no. 109-2221-E-224-042).

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Authors and Affiliations

  1. National Yunlin University of Science and Technology, Douliu, Taiwan

    Shih-Chang Hsia, Szu-Hong Wang & Ting-Tseng Kuo

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  1. Shih-Chang Hsia
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  2. Szu-Hong Wang
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  3. Ting-Tseng Kuo
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Correspondence to Shih-Chang Hsia.

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Hsia, SC., Wang, SH. & Kuo, TT. VLSI architecture and implementation of HDR camera signal processor. J Real-Time Image Proc 20, 6 (2023). https://doi.org/10.1007/s11554-023-01262-2

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