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Performance comparison of throughput between AVC, HEVC and VVC hardware CABAC decoder

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Abstract

This paper proposes a performance comparison of throughput between context-based adaptive binary arithmetic decoding (CABAC) processes adopted in the three recent video codecs: advanced video coding (AVC), high efficiency video coding (HEVC), and versatile video coding (VVC). Consequently, in order to highlight the performance and the modification in three CABAC versions: the three main stages of CABAC decoding Context Selection and Modeling (CSM), Binary Arithmetic Decoding (BAD) and De-binarization (DBZ) are designed, described in VHDL language and implemented on Field Programmable Gate Array (FPGA) device. Firstly, the most efficient CSM is obtained for CABAC VVC with maximum frequency of 183.8 MHz and low power consumption of 0.346 mW. Secondly, the BAD in RM is modified only in the last video standard VVC. The most efficient design of BAD RM is given in the AVC and HEVC version of CABAC with maximum frequency of 261.75 MHz. Thirdly, the BAD in BM and TM are the same adopted in the three CABAC version, with maximum frequencies of 439.657 MHz and 798.861 MHz, respectively. Thirdly, the de-binarization codes are also the same adopted in the three last CABAC versions. Consequently, high frequency of 789.26 MHz is obtained in DBZ but the resources cost and power consumption are greater than that given in CSM and BAD stages. Finally, high throughput of 178.13 bins/s is given by our proposed design of VVC CABAC decoder.

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References

  1. Sullivan, G.J., Ohm, J.-R., Han, W.-J., Wiegand, T.: Overview of the high efficiency video coding (HEVC) standard. IEEE Trans. Circuits Syst. Video Technol. 22(12), 1649–1668 (2012)

    Article  Google Scholar 

  2. Information technology: Coded representation of immersive media—part 3: versatile video coding. ISO/IEC DIS 23090-3 (2020)

  3. Bross, B., Chen, J., Liu, S.: Versatile Video Coding (Draft 4), document JVET-M1001. In: 13th JVET meeting, pp. 9–18. Marrakech, MA, USA (2019).

  4. Menasri, W., Skoudarli, A., Belhadj Aissa, A.: Implementation of multi-bin CABAC decoder in HEVC/H.265 on FPGA, CSA’2018 conference. Springer, Algiers (2018).

  5. Wang, M.-Z., Wan, S., Gong, H., Ma, M.: Attention-based dual-scale CNN in-loop filter for versatile video coding. IEEE Access 7, 145214–145226 (2019)

    Article  Google Scholar 

  6. Telecommunication standardization sector of ITU: Series H: Audiovisual and multimedia systems, Infrastructure of audiovisual services-coding of moving video (High efficiency video coding), H.265 12/2016.

  7. Telecommunication standardization sector of ITU: Series H: Audiovisual and multimedia systems, Infrastructure of audiovisual services-Coding of moving video (Versatile video coding), H.266 08/2020.

  8. Telecommunication standardization sector of ITU: Series H: Audiovisual and multimedia systems, Infrastructure of audiovisual services-coding of moving video (Advanced video coding), H.264 04/2007.

  9. Saldanha, M., Corrêa, M., Corrêa, G., Palomino, D., Porto, M., Zatt, B., Agostini, L.: An overview of dedicated hardware designs for state-of-the-art AV1 and H.266/VVC video codecs. IEEE (2020).

  10. Park, S.-H., Kang, J.-W.: Context-based ternary tree decision method in versatile video coding for fast intra coding. IEEE Access 7, 172597–172605 (2019)

    Article  Google Scholar 

  11. Menasri, W., Skoudarli, A., Belhadj, A., Azzaz, M.: Field programmable gate array implementation of variable-bins high efficiency video coding CABAC decoder with path delay optimisation. IET Image Process. 13(6), 954–963 (2019)

    Article  Google Scholar 

  12. Korishetti, A.C., Malemath, V.S.: Regressive rate-distortion trade-off with weighted entropy coding for HEVC encoding. J. Real Time Image Proc. 18, 2165–2180 (2021). https://doi.org/10.1007/s11554-01096-WD

    Article  Google Scholar 

  13. Marpe, H.S., Wiegand, T.: Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard. IEEE Trans. Circuits Syst. Video Technol. 13(7), 620–636 (2003)

    Article  Google Scholar 

  14. Fei, W., Zhou, D., Goto, S.: 1 Gbin/s CABAC encoder for H.264/AVC. In: Proceedings of the 19th European Signal Processing Conference (EUSIPCO), pp. 1524–1528. Barcelona, Spain (2011)

  15. Zhou, J., Zhou, D., Fei, W., Goto, S.: A high-performance CABAC encoder architecture for HEVC and H.264/AVC. In: Proceedings of the IEEE International Conference on Image Processing (ICIP), pp. 1568–1572. Melbourne, Australia.

  16. Zhou, D., Zhou, J., Fei, W., Goto, S.: Ultra-high-throughput VLSI architecture of H.265/HEVC CABAC encoder for UHDTV applications. IEEE Trans. Circuits Syst. Video Technol. (TCSVT) 25(3), 497–507 (2015)

    Article  Google Scholar 

  17. Ramos, F.L.L., Zatt, B., Porto, M.S., Bampi, S.: High-throughput binary arithmetic encoder using multiple-bypass bins processing for HEVC CABAC. In: Proceedings of the IEEE international symposium on circuits and systems (ISCAS), pp. 1–5. Florence, Italy, (2018).

  18. Ramos, F.L.L., Zatt, B., Porto, M., Bampi, S.: Energy-throughput configurable design for video processing binary arithmetic encoder. IEEE Trans. Circuits Syst. Video Technol. 31(3), 1163–1177 (2020)

    Article  Google Scholar 

  19. Kim, D., Moon, J., Lee, S.: Hardware implementation of HEVC CABAC context modeler. J. IKEEE 19(2), 254–259 (2015)

    Article  Google Scholar 

  20. Kim, S., Kim, D., Lee, S.: Hardware implementation of context modeler in HEVC CABAC decoder. J. IKEEE 21(3), 280–283 (2017)

    Google Scholar 

  21. Mamidi, N., Gupta, S.K., Bhadauria, V.: Design and implementation of parallel bypass bin processing for CABAC encoder. Adv Electr Electron Eng 19(3), 243–257 (2021)

    Google Scholar 

  22. Osorio, R.R., Bruguera, J.D.: High-speed FPGA architecture for CABAC decoding acceleration in H. 264/AVC standard. J. Signal. Process. Syst. 72(2), 119–132 (2013)

    Article  Google Scholar 

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Correspondence to Wahiba Menasri.

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Menasri, W., Skoudarli, A. Performance comparison of throughput between AVC, HEVC and VVC hardware CABAC decoder. J Real-Time Image Proc 20, 26 (2023). https://doi.org/10.1007/s11554-023-01266-y

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