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Low-cost low-power approximated VLSI architecture for high-quality image scaling in mobile devices

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Abstract

This paper proposes three pipeline VLSI architectures for high-quality image scaling. The proposed architectures use low-complexity v-model spatial sharpening filter, modified edge detection, and simplified bilinear interpolation. Low complexity v-model spatial sharpening filter is obtained by modifying the 3 \(\times\) 3 sharpening kernel to x-model and then to v-model. This sharpening filter enhances the center pixel intensity value relative to the nearest pixels. The modified edge detection technique needs less hardware to find the sharp change in the pixel values. The number of multipliers required for bilinear interpolation is reduced by performing algebraic manipulations. Matlab tool is used analyze the scaled image quality with Peak Signal to Noise Ratio (PSNR) and Structural Similarity (SSIM) parameters. The proposed three VLSI architectures are described using Verilog HDL (hardware description language) and synthesized using Cadence genus compiler using GPDK 90 nm technology. One of the proposed architectures requires 8981 (µm2) area and consumes 1.90 (mW) power, which is less when compared to those of the existing architectures.

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Acknowledgements

The authors would like to thank SMDP-C2SD Project, NIT Calicut, funded by MeitY, Govt. of India, for providing research facility and technical support.

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  1. National Institute of Technology Calicut, Calicut, Kerala, India

    Venkata Siva Midde & E. P. Jayakumar

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  1. Venkata Siva Midde
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Midde, V.S., Jayakumar, E.P. Low-cost low-power approximated VLSI architecture for high-quality image scaling in mobile devices. J Real-Time Image Proc 20, 11 (2023). https://doi.org/10.1007/s11554-023-01282-y

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