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FPGA acceleration of secret sharing for 3D data cubes

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Abstract

Secret sharing can protect the security of important secret information in the network environment. However, the computational complexity and processing delay increase drastically when the secret information contains large amounts of data, such as three-dimensional (3D) data cubes. To improve the efficiency of secret sharing on 3D data cubes, this paper proposes a hardware architecture to accelerate the generation of shares and reconstruction of the secret. The proposed hardware architecture parallelizes the secret sharing process and optimizes on this basis to save large amounts of circuit resources. Simulation results show that this architecture performs secret sharing more than ten times faster than the software implementation. This study enables the secret sharing of 3D data cubes, which protect large amounts of data information throughout the process and allows complete reconstruction of 3D data cubes. To be able to handle secrets without decoding them, we then extend the hardware architecture to the four basic processes of multi-party computation, demonstrating the feasibility of the structure and providing preliminary research tools for the effective implementation of multi-party computation.

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Data availability

The data used in this study are available from the corresponding author upon request.

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Acknowledgements

This work was funded by the Shandong Provincial Natural Science Foundation (No. ZR2021MF050), the Ministry of Education in China (MOE) Project of Humanities and Social Sciences (Project No. 18YJAZH110), and the National Statistics Science Project (2021LY082).

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Authors and Affiliations

  1. College of Electronic and Information Engineering, Shandong University of Science and Technology, Qingdao, 266590, Shandong, People’s Republic of China

    Zi-Ming Wu, Tao Liu, Bin Yan, Jeng-Shyang Pan & Hong-Mei Yang

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  1. Zi-Ming Wu
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  2. Tao Liu
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  3. Bin Yan
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  4. Jeng-Shyang Pan
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  5. Hong-Mei Yang
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Contributions

All authors contributed to the study conception and design. Material preparation, data collection and analysis were performed by TL, BY, J-SP and H-MY. The first draft of the manuscript was written by Z-MW and all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript.

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Correspondence to Bin Yan.

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Wu, ZM., Liu, T., Yan, B. et al. FPGA acceleration of secret sharing for 3D data cubes. J Real-Time Image Proc 20, 82 (2023). https://doi.org/10.1007/s11554-023-01337-0

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