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Scalable and custom-precision floating-point hardware convolution core for using in AI edge processors

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Abstract

AI algorithms such as CNNs devices have necessitated the design of lightweight, low-power, and fast hardware in edge processors. In this paper, a floating-point convolution core is proposed for edge processors to implement CNN. At first, the conventional CNN networks were analyzed in terms of the abundance of filter size. Considering the performance and execution time, the focus of the research is on size of 3 × 3. Next, using the proposed 10-input adder instead of nine 2-input adders and modifying the multipliers, an optimum 32-bit 3 × 3 convolution core has been designed. After studying different bit widths in mantissa and the exponent of floating-point numbers in CNNs, 13-bit is considered as the minimum bit width without accuracy losing. The 3 × 3 core with the new bit width is implemented. Since filter sizes 1 × 1 and 5 × 5 are also available in conventional networks, the new scalable architecture is designed to support all three sizes. Finally, the YOLOv4-tiny object detection and GoogLeNet are used as two benchmarks to evaluate the final 3 × 3 scalable core. The results have shown that despite using floating-point calculations, the FPS is equal to 45.9, which is equal to the previous works that were done in fixed-point, while the accuracy of the proposed work is 84% which is similar to the 32-bit floating point.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Hormozgan, Bandar Abbas, Iran

    Mahdi Shafiei, Hassan Daryanavard & Ahmad Hatam

Authors
  1. Mahdi Shafiei
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  2. Hassan Daryanavard
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  3. Ahmad Hatam
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Contributions

Mr. Daryanvard presented the main ideas of the paper, and Mr. Shafiei did the simulations. Mr. Daryanavard wrote the paper. Edited by Mr. Hatem. All authors reviewed the manuscript.

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Correspondence to Hassan Daryanavard.

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Shafiei, M., Daryanavard, H. & Hatam, A. Scalable and custom-precision floating-point hardware convolution core for using in AI edge processors. J Real-Time Image Proc 20, 94 (2023). https://doi.org/10.1007/s11554-023-01352-1

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