Abstract
This manuscript proposes a low-power and high-speed hybrid approximate multiplier using 15-4 approximate compressors in partial product stage for image processing application. Initially, the most significant bits (MSB) of approximate multiplier is encoded by approximate radix-8 Booth’s (R-8B) encoding, and also least significant bits (LSB) is encoded by approximate truncated-round approximate multiplier (TRAM) encoding both are used to rounding the LSB to the adjacent power of two. Then, approximate 15-4 compressors are subjugated in partial product lessening stage to produce MSB result. Then, the hybrid approximate multiplier under 15-4 approximate compressors is carried out in the application of image processing. The proposed approach is done in MATLAB and Vivado Design Suite 2018.1 simulator, then observes that the power consumption of proposed design attains 31.814%, 23.562% lower than existing models. Similarly, the velocity attains 42.63%, 6.263% higher than the existing models.
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References
Parihar, A., Nakhate, S.: High-speed high-throughput VLSI architecture for RSA montgomery modular multiplication with efficient format conversion. J. Inst. Eng. (India): Ser. B 100, 217–222 (2019)
Cao, T., Liu, Y.J., Jiang, J., Zhang, Q., Lin, C., Yang, D., Zhou, J.: Frequency multiplier-based millimeter-wave vector signal transmitter using digital predistortion with constrained feedback bandwidth. IEEE Trans. Microw. Theory Tech. 68(5), 1819–1829 (2020)
Mariya Priyadarshini, K., Ernest Ravindran, R.S., Atindra Chandra Sekhar, M., Sai Kalyan, P.J.V., Rahul, G.: A high-speed precision-controllable approximate 16 bit multiplier. Int. J. Adv. Sci. Technol. 28(20), 31–41 (2019)
Ernest Ravindran, R.S., Priyadarshini, K.M., Sai, A.T., Shiny, P., Sabeena, S.: Design of finite field multiplier for efficient data encryption. Int. J. Adv. Sci. Technol. 28(20), 42–52 (2019)
Shajin, F.H., Rajesh, P., Raja, M.R.: An efficient VLSI architecture for fast motion estimation exploiting zero motion prejudgment technique and a new quadrant-based search algorithm in HEVC. Circuits Syst. Signal Process. 41, 1–24 (2022)
Ahmadinejad, M., Moaiyeri, M.H.: Energy-and quality-efficient approximate multipliers for neural network and image processing applications. IEEE Trans. Emerg. Top. Comput. 10(2), 1105–1116 (2021)
Prashanth, H.C., Gowda Bindu, G., Rao, M.,: Design and evaluation of in-exact compressor based approximate multipliers. In: Proceedings of the Great Lakes Symposium on VLSI 2022, Association for Computing Machinery pp. 431–436 (2022)
Verma, A., Khan, A., Wairya, S.: Design and analysis of efficient Vedic multiplier for fast computing applications. Int. J. Comput. Digit. Syst. 13(1), 190–201 (2023)
Kumar, U.A., Chatterjee, S.K., Ahmed, S.E.: Low-power compressor-based approximate multipliers with error correcting module. IEEE Embed. Syst. Lett. 14(2), 59–62 (2021)
Meenaakshi Sundhari R.P. : An efficient implementation of low‐power approximate compressor-based multiplier for cognitive communication systems. Int. J. Commun. Syst. 35(2), e4180 (2022)
Locharla, G.R., Mahapatra, K.K., Ari, S.: Radix-8 modified Booth fixed-width signed multipliers with error compensation. Arab. J. Sci. Eng. 46, 1115–1125 (2021)
Leon, V., Zervakis, G., Soudris, D., Pekmestzi, K.: Approximate hybrid high radix encoding for energy-efficient inexact multipliers. IEEE Trans. Very Large Scale Integr. Syst. 26(3), 421–430 (2017)
Lotrič, U., Pilipović, R., Bulić, P.: A hybrid radix-4 and approximate logarithmic multiplier for energy efficient image processing. Electronics 10(10), 1175 (2021)
Immareddy, S., Sundaramoorthy, A., Alagarsamy, A.: Adaptive FIR filter design with approximate adder and hybridized multiplier for efficient noise eradication in sensor nodes. ECS J. Solid State Sci. Technol. 12(9), 097002 (2023)
Mahendran, P., Kavitha, M.S., Radhika, R., Kotteeswaran, C.: Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application. Concurr. Comput.: Pract. Exp. 35(6), 1–1 (2023)
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Mr. Srikanth Immareddy—(corresponding author)—conceptualization methodology, and original draft preparation. Dr. Arunmetha Sundaramoorthy—Supervision. Dr. Aravindhan Alagarsamy—Supervision.
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Immareddy, S., Sundaramoorthy, A. & Alagarsamy, A. Design and implementation of hybrid (radix-8 Booth and TRAM) approximate multiplier using 15-4 approximate compressors for image processing application. J Real-Time Image Proc 21, 50 (2024). https://doi.org/10.1007/s11554-024-01427-7
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DOI: https://doi.org/10.1007/s11554-024-01427-7