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An ILP based hierarchical global routing approach for VLSI ASIC design

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Abstract

The use of integrated circuits in high-performance computing, telecommunications, and consumer electronics has been growing at a very fast pace. The level of integration as measured by the number of logic gates in a chip has been steadily rising due to the rapid progress in processing and interconnect technology. The interconnect delay in VLSI circuits has become a critical determiner of circuit performance. As a result, circuit layout is starting to play a more important role in today’s chip designs. Global routing is one of the key sub-problems of circuit layout which involves finding an approximate path for the wires connecting the elements of the circuit without violating resource constraints. In this paper, several integer programming (ILP) based global routing models are fully investigated and explored. The resulting ILP problem is relaxed and solved as a linear programming (LP) problem followed by a rounding heuristic to obtain an integer solution. Experimental results obtained show that the proposed combined WVEM (wirelength, via, edge capacity) model can optimize several global routing objectives simultaneously and effectively. In addition, several hierarchical methods are combined with the proposed flat ILP based global router to reduce the CPU time by about 66% on average for edge capacity model (ECM).

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References

  1. Behjat, L.: New modeling and optimization techniques for the global routing problem. PhD thesis, University of Waterloo, ON, Canada (2002)

  2. Cheng, L., Song, X.Y., Yang, G.W., Tang, Z.W.: A fast congestion estimator for routing with bounded detours. In: Proceedings of the 2004 conference on Asia South Pacific design automation, pp. 666–670 (2004)

  3. Chen, T., Chang, Y.: Multilevel full-chip gridless routing considering optical proximity correction. In: Proceedings of the 2005 conference on Asia South Pacific design automation, pp. 1160–1163 (2005)

  4. Chen, T., Chang, Y., Lin, S.: A novel framework for multilevel full-chip gridless routing. In: Proceedings of the 2006 conference on Asia South Pacific design automation, pp. 636–641 (2006)

  5. Cong J., Fang J., Zhang Y. (2005): MARS-A multilevel full-chip gridless routing system. IEEE Trans. Comput. Aided Des. 24, 382–394

    Article  Google Scholar 

  6. Hadsell, R.T., Madden, P.H.: Improved global routing through congestion estimation. In: Proceedings of the 40th DAC, pp. 28–34, IEEE/ACM, Anaheim, CA (2003)

  7. Kang S.-M., Leblebici Y. (2003): CMOS Digital Integrated Circuits. McGraw-Hill, New York

    Google Scholar 

  8. S. L., Chang, Y.: A novel framework for multilevel routing considering routability and performance. In: Proceedings of the 2002 International Conference on Computer Aided Design, pp. 44–50 (2002)

  9. Lou, J., Krishnamoorthy, S., Sheng, H.S.: Estimating routing congestion using probabilistic analysis. In: International Symposium on Physical Design, pp. 112–117 (2001)

  10. MCNC: www.cbl.ncsu.edu/benchmarks/layoutsynth92/ (1991)

  11. Sherwani N. (1999): Algorithms for VLSI Physical Design Automation. Kluwer, Boston

    MATH  Google Scholar 

  12. Vannelli A. (1991): An adaptation of the interior point method for solving the global routing problem. IEEE Trans. Comput. Aided Des. 10, 193–203

    Article  Google Scholar 

  13. Warme, D.M.: A new exact algorithm for rectilinear steiner trees. In: International Symposium on Mathematical Programming (1997)

  14. Yang, Z., Areibi, S., Vannelli, A.: An ILP based hierarchical global routing approach for VLSI ASIC design. University of Waterloo, Technical Report, University of Waterloo, Waterloo, ON, (2006)

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Authors and Affiliations

  1. Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, N2L 3G1, Canada

    Zhen Yang & Anthony Vannelli

  2. Engineering System and Computing, University of Guelph, Guelph, ON, N1G 2W1, Canada

    Shawki Areibi

Authors
  1. Zhen Yang
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  2. Anthony Vannelli
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  3. Shawki Areibi
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Correspondence to Zhen Yang.

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Yang, Z., Vannelli, A. & Areibi, S. An ILP based hierarchical global routing approach for VLSI ASIC design. Optimization Letters 1, 281–297 (2007). https://doi.org/10.1007/s11590-006-0027-0

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  • DOI: https://doi.org/10.1007/s11590-006-0027-0

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