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Minimizing interconnect length on reconfigurable meshes

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Abstract

Shorter total interconnect and fewer switches in a processor array definitely lead to less capacitance, power dissipation and dynamic communication cost between the processing elements. This paper presents an algorithm to find a maximum logical array (MLA) that has shorter interconnect and fewer switches in a reconfigurable VLSI array with hard/soft faults. The proposed algorithm initially generates the middle (⌊k/2⌋th) logical column and then makes it nearly straight for the MLA with k logical columns. A dynamic programming approach is presented to compact other logical columns toward the middle logical column, resulting in a tightly-coupled MLA. In addition, the lower bound of the interconnect length of the MLA is proposed. Experimental results show that the resultant logical array is nearly optimal for the host array with large fault size, according to the proposed lower bound.

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Authors and Affiliations

  1. School of Computer Science and Software, Tianjin Polytechnic University, Tianjin, 300160, China

    Jigang Wu

  2. School of Computer Engineering, Nanyang Technological University, Singapore, 639798, Singapore

    Jigang Wu, Thambipillai Srikanthan & Kai Wang

Authors
  1. Jigang Wu
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  2. Thambipillai Srikanthan
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  3. Kai Wang
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Correspondence to Jigang Wu.

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Wu, J., Srikanthan, T. & Wang, K. Minimizing interconnect length on reconfigurable meshes. Front. Comput. Sci. China 3, 315–321 (2009). https://doi.org/10.1007/s11704-009-0032-4

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  • DOI: https://doi.org/10.1007/s11704-009-0032-4

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