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Exploring system architectures in AADL via Polychrony and SynDEx

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Abstract

Architecture analysis & design language (AADL) has been increasingly adopted in the design of embedded systems, and corresponding scheduling and formal verification have been well studied. However, little work takes code distribution and architecture exploration into account, particularly considering clock constraints, for distributed multi-processor systems. In this paper, we present an overview of our approach to handle these concerns, together with the associated toolchain, AADL-Polychrony-SynDEx. First, in order to avoid semantic ambiguities of AADL, the polychronous/multiclock semantics of AADL, based on a polychronous model of computation, is considered. Clock synthesis is then carried out in Polychrony, which bridges the gap between the polychronous semantics and the synchronous semantics of SynDEx. The same timing semantics is always preserved in order to ensure the correctness of the transformations between different formalisms. Code distribution and corresponding scheduling is carried out on the obtained SynDEx model in the last step, which enables the exploration of architectures originally specified in AADL. Our contribution provides a fast yet efficient architecture exploration approach for the design of distributed real-time and embedded systems. An avionic case study is used here to illustrate our approach.

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Authors and Affiliations

  1. INRIA Rennes — Bretagne Atlantique, 263, av. du Général Leclerc, Rennes, 35042, France

    Huafeng Yu, Yue Ma, Thierry Gautier, Jean-Pierre Talpin & Paul Le Guernic

  2. IRISA/CNRS, 263, av. du Général Leclerc, Rennes, 35042, France

    Loïc Besnard

  3. INRIA Paris — Rocquencourt, Domaine de Voluceau, BP 105, Le Chesnay Cedex, 78153, France

    Yves Sorel

Authors
  1. Huafeng Yu
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  2. Yue Ma
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  3. Thierry Gautier
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  4. Loïc Besnard
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  5. Jean-Pierre Talpin
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  6. Paul Le Guernic
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  7. Yves Sorel
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Corresponding author

Correspondence to Thierry Gautier.

Additional information

Huafeng Yu has been an expert research engineer within INRIA Rennes, France. His work is involved in timing analysis, formal verification, simulation, and synthesis of MARTE-based timed systems, AADL, and Simulink in the framework of several European projects, such as CESAR and OPEES. He completed his Master’s study in Systems and Software at Université Joseph Fourier Grenoble 1 (France) in 2005. He received his PhD in Computer Science from Université des Sciences et Technologies de Lille (France) in 2008. He is now working in Toyota InfoTechnology Center USA as a senior researcher. His main research interests include model-based systems engineering, automotive and aerospace engineering, embedded systems design, formal methods, and synchronous languages.

Yue Ma has been a post-doc fellow in IRISA/INRIA Rennes, France. She works on the modeling, temporal analysis, formal verification and simulation of globally asynchronous locally synchronous systems, especially AADL using polychrony in the framework of European TopCased, CESAR and OPEES projects. She received her PhD in Computer Science from University of Rennes 1 (France) in 2010. She is now working in itemis France as a senior software architect. Her research interests include software engineering, embedded systems design, synchronous programming, AADL modeling and analysis, automotive engineering, such as AUTOSAR and EAST-ADL.

Thierry Gautier is a researcher with INRIA. He received the graduate degree from the Institut National des Sciences Appliqu’ees, Rennes, France, in 1980, and the PhD in Computer Science from Université de Rennes 1 in 1984. He is one of the designers of the signal language, the polychronous model of computation and the Polychrony toolset. His main research interests lie in the safe design of complex embedded systems, including formal modeling, formal validation, and transformations of models to target architectures.

Loïc Besnard is currently a senior engineer at CNRS, France. He received his PhD in Computer Science from Université de Rennes, France (1992). His research interests include the software reliability for the design of embedded systems: modeling, temporal analysis, formal verification, simulation, and synthesis of embedded systems. He is involved in the development of the polychony toolset based on the synchronous language signal.

Jean-Pierre Talpin is a senior researcher with INRIA and leads the project-team who develops the open-source polychrony environment. He received his PhD from Université Paris VI Pierre et Marie Curie in 1993. He then was a research associate with the European Computer-Industry Research Centre in Munich before to join INRIA in 1995. Jean-Pierre edited two books with Elsevier and Springer, guest-edited more than ten special issues of ACM and IEEE scientific journals, and authored more than 20 journal articles and book chapters and 60 conference papers. He received the 2004 ACM Award for the most influential POPL paper, for his 2nd conference paper with Mads Tofte, and the 2012 LICS Test of Time Award, for his 1st conference paper with Pierre Jouvelot.

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Yu, H., Ma, Y., Gautier, T. et al. Exploring system architectures in AADL via Polychrony and SynDEx . Front. Comput. Sci. 7, 627–649 (2013). https://doi.org/10.1007/s11704-013-2307-z

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