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Design and implementation of anchor coprocessor architecture for wireless node localization applications

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Abstract

Localization systems should be as robust, accurate, and energy-efficient as possible in a wireless sensor network. A centralized localization scheme using a mobile anchor avoids computational overhead at resource-constrained nodes, which improves network lifetime by reducing power consumption. The anchor plays a vital role in accurately estimating the positions of the nodes in the network. Equipping a GPS (Global Positioning System) receiver, an anchor provides reference information to position computation by trilateration or triangulation. Therefore, an anchor coprocessor on dedicated hardware performs the localization faster with low power consumption. In this work, we proposed a localization method in which an anchor centrally computes node positions based on RSS (Received Signal Strength) and AoA (Angle of Arrival) information. We also presented the custom design of anchor coprocessor architecture using the appropriate FSMD (Finite State Machine with Datapath) models and CORDIC (COordinate Rotation DIgital Computer) blocks. The anchor moves along a random path in the network and performs clustering of some neighboring nodes with RSS exceeding a prescribed threshold using a smart antenna. The coprocessor estimates localization information (distance and angle) for the clustering nodes at two distinct anchor points and keeps them in a table. It then computes the positions for nodes encountered twice in the table. Coprocessor performance is tested on a dedicated FPGA (Field Programmable Gate Array) board with multiple fixed-point hardware-level simulations for localization accuracy, computational complexities, and power consumption. The results are comparable to existing systems and corroborate implementation feasibility on wireless network infrastructure with limited resources.

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Data availability

The datasets generated during the current study are available from the corresponding author on reasonable request.

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Acknowledgements

The authors would like to express their gratitude to the esteemed editors and all anonymous reviewers for their valuable suggestions and comments to improve the quality of this paper.

Funding

No funding was received for conducting this study.

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Author notes

  1. Rathindra Nath Biswas, Anurup Saha and Swarup Kumar Mitra contributed equally to this work.

Authors and Affiliations

  1. Department of ETCE, Central Calcutta Polytechnic, Kolkata, 700014, West Bengal, India

    Rathindra Nath Biswas

  2. Department of ETCE, Jadavpur University, Kolkata, 700032, West Bengal, India

    Anurup Saha & Mrinal Kanti Naskar

  3. Department of ECE, Guru Nanak Institute of Technology, Kolkata, 700114, West Bengal, India

    Swarup Kumar Mitra

Authors
  1. Rathindra Nath Biswas
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  2. Anurup Saha
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  4. Mrinal Kanti Naskar
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Contributions

Rathindra Nath Biswas wrote the main manuscript text including all figures and tables. Anurup Saha and Swarup Kumar Mitra performed experimentation on FPGA to get results. Mrinal Kanti Naskar reviewed the manuscript.

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Correspondence to Mrinal Kanti Naskar.

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Biswas, R.N., Saha, A., Mitra, S.K. et al. Design and implementation of anchor coprocessor architecture for wireless node localization applications. Peer-to-Peer Netw. Appl. 17, 961–984 (2024). https://doi.org/10.1007/s12083-024-01640-y

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