Abstract
Network-on-chip (NoC) has been introduced to increase the performance of chip multiprocessors (CMPs) and execute parallel programs. Although NoC is known as a modular and scalable infrastructure for interconnections, there are still some challenges with conventional NoC such as high latency and power consumption due to the communication among long-distance (LD) cores. In this regard, wireless network-on-chip (WiNoC) is a potential solution that can provide high bandwidth and low latency by means of the unique features of wireless interconnects. However, wireless routers (WRs) are prone to congestion in WiNoC due to the limited number of wireless channels on a chip and shared use of these channels by all processing elements (PEs). In this study, a load-balanced time-based congestion-aware (LTCA) routing algorithm is proposed to eliminate the congestion of WRs and distribute the traffic load on the wired and wireless networks in a balanced way. LTCA is a deadlock-free routing algorithm in which only a limited number of packets are allowed to use wireless channels. The required time for transmitting the selected packets through wireless links is measured with regard to the bandwidth of the wireless channels and traffic load. Simulation results on synthetic traffic patterns and real-world 3-tuple traffic patterns indicated a considerable improvement in latency, throughput, wired and wireless link utilization and packet loss probability.
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References
Abadal S, Torrellas J, Alarcón E, Cabellos-Aparicio A (2018) OrthoNoC: a broadcast-oriented dual-plane wireless network-on-chip architecture. IEEE Trans Parallel Distrib Syst 29:628–641. https://doi.org/10.1109/TPDS.2017.2764901
Bahrami B, Jamali MAJ, Saeidi S (2016) Proposing an optimal structure for the architecture of wireless networks on chip. Telecommun Syst 62:199–214. https://doi.org/10.1007/s11235-015-0075-9
Bansal A, Gupta A, Sharma DK, Gambhir V (2018) IICAR-inheritance inspired context aware routing protocol for opportunistic networks. J Ambient Intell Humaniz Comput. https://doi.org/10.1007/s12652-018-0815-2
Ben-Itzhak Y, Zahavi E, Cidon I, Kolodny A (2012) HNOCS: modular open-source simulator for heterogeneous NoCs. In: Proceedings of 2012 international conference on embedded computer systems architecture, modelling and simulations IC-SAMOS. pp 51–57. https://doi.org/10.1109/SAMOS.2012.6404157
Carvalho ELdS, Calazans NLV, Moraes FG (2010) Dynamic task mapping for MPSoCs. IEEE Des Test Comput 27:26–35
Chen G, Anders MA, Kaul H et al (2015) A 340 mV-to-0.9 V 20.2 Tb/s source-synchronous hybrid packet/circuit-switched 16 × 16 network-on-chip in 22 nm tri-gate CMOS. IEEE J Solid State Circuits 50:59–67
Chou C-L, Marculescu R (2008) Contention-aware application mapping for network-on-chip communication architectures. In: ICCD 2008, IEEE international conference on computer design, pp 164–169
Dally WJ, Towles BP (2004) Principles and practices of interconnection networks. Morgan Kaufmann Publishers Inc., San Francisco
Davis WR, Wilson J, Mick S et al (2005) Demystifying 3D ICs: the pros and cons of going vertical. IEEE Des Test Comput 22:498–510. https://doi.org/10.1109/MDT.2005.136
Deb S, Chang K, Yu X et al (2013) Design of an energy-efficient CMOS-compatible NoC architecture with millimeter-wave wireless interconnects. IEEE Trans Comput 62:2382–2396
DiTomaso D, Kodi A, Kaya S, Matolak D (2011) IWISE: Inter-router wireless scalable express channels for network-on-chips (NoCs) architecture. In: Proceeding of symposium on high perform interconnects hot interconnects, pp 11–18. https://doi.org/10.1109/HOTI.2011.12
DiTomaso D, Kodi A, Matolak D et al (2015) A-WiNoC: adaptive wireless network-on-chip architecture for chip multiprocessors. IEEE Trans Parallel Distrib Syst 26:3289–3302. https://doi.org/10.1109/TPDS.2014.2383384
Duraisamy K, Xue Y, Bogdan P, Pande PP (2017) Multicast-aware high-performance wireless network-on-chip architectures. IEEE Trans Very Large Scale Integr Syst 25:1126–1139
Fattah M, Ramirez M, Daneshtalab M et al (2012) CoNA: dynamic application mapping for congestion reduction in many-core systems. In: Computer design (ICCD), 2012 IEEE 30th international conference, pp 364–370
Fattah M, Daneshtalab M, Liljeberg P, Plosila J (2013) Smart hill climbing for agile dynamic mapping in many-core systems. In: Proceedings of the 50th annual design automation conference, ACM, New York, NY, USA, p 39:1–39:6
Howard J, Dighe S, Vangal SR et al (2011) A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling. IEEE J Solid State Circuits 46:173–183
Hu W-H, Wang C, Bagherzadeh N (2015) Design and analysis of a mesh-based wireless network-on-chip. J Supercomput 71:2830–2846. https://doi.org/10.1007/s11227-014-1341-4
Kempa K, Rybczynski J, Huang Z et al (2007) Carbon nanotubes as optical antennae. Adv Mater 19:421–426. https://doi.org/10.1002/adma.200601187
Lee S-B, Zhang L, Cong J et al (2009) A scalable micro wireless interconnect structure for CMPs. In: Proceedings of 15th annual international conference on mobile computing and networking—MobiCom’09 217. https://doi.org/10.1145/1614320.1614345
Lin JJ, Wu HT, Su Y et al (2007) Communication using antennas fabricated in silicon integrated circuits. IEEE J Solid State Circuits 42:1678–1687
Matolak DW, Kodi A, Kaya S et al (2012) Wireless networks-on-chips: architecture, wireless channel, and devices. IEEE Wirel Commun 19:58–65. https://doi.org/10.1109/MWC.2012.6339473
Murray J, Wettin P, Pande PP, Shirazi B (2016a) Sustainable wireless network-on-chip architectures. Morgan Kauffmann, Cambridge, pp 1–9. https://doi.org/10.1016/B978-0-12-803625-9.00008-X
Murray J, Wettin P, Pande PP, Shirazi B (2016b) Wireless small-world NoCs. In: wireless network-on-chip architectures, pp 37–45. https://doi.org/10.1016/B978-0-12-803625-9.00011-X
Qiuli C, Wei X, Fei D, Ming H (2018) A reliable routing protocol against hotspots and burst for UASN-based fog systems. J Ambient Intell Humaniz Comput. https://doi.org/10.1007/s12652-018-0810-7
Rayess W, Matolak DW, Kaya S, Kodi AK (2017) Antennas and channel characteristics for wireless networks on chips. Wirel Pers Commun. https://doi.org/10.1007/s11277-017-4144-0
Rezaei A, Daneshtalab M, Zhao D et al (2015) Dynamic application mapping algorithm for wireless network-on-chip. In: Proceeding of 23rd Euromicro international conference on parallel, distributed and network-based processing (PDP), 2015, pp 421–424. https://doi.org/10.1109/PDP.2015.14
Rezaei A, Daneshtalab M, Palesi M, Zhao D (2016) Efficient congestion-aware scheme for wireless on-chip networks. In: 2016 24th Euromicro international conference on arallel, distributed, and network-based processing, pp 742–749. https://doi.org/10.1109/PDP.2016.88
Rezaei A, Daneshtalab M, Zhao D (2017) CAP-W: congestion-aware platform for wireless-based network-on-chip in many-core era. Microprocess Microsyst 52:23–33. https://doi.org/10.1016/j.micpro.2017.05.014
Soteriou V, Eisley N, Wang H et al (2006) Polaris: a system-level roadmap for on-chip interconnection networks. In: IEEE international conference on computer design, ICCD, 2006, pp 134–141. https://doi.org/10.1109/ICCD.2006.4380806
Vantrease D, Schreiber R, Monchiero M et al (2008) Corona: system implications of emerging nanophotonic technology. In: Proceedings of international symposium on computer architecture, pp 153–164. https://doi.org/10.1109/ISCA.2008.35
Wang C, Hu WH, Bagherzadeh N (2012) A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms. Microprocess Microsyst 36:555–570. https://doi.org/10.1016/j.micpro.2011.10.002
Wettin P, Kim R, Murray J et al (2014) Design space exploration for wireless NoCs incorporating irregular network routing. IEEE Trans Comput Des Integr Circuits Syst 33:1732–1745. https://doi.org/10.1109/TCAD.2014.2351577
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Mikaeeli Mamaghani, S., Jabraeil Jamali, M.A. A load-balanced congestion-aware routing algorithm based on time interval in wireless network-on-chip. J Ambient Intell Human Comput 10, 2869–2882 (2019). https://doi.org/10.1007/s12652-018-1020-z
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DOI: https://doi.org/10.1007/s12652-018-1020-z