Abstract
Application graph mapping is one of the hardest and time-consuming problems in interconnection networks. Although many approaches are targeting the quality of the solution, one fast and accurate algorithm for solving this kind of problem is needed strongly. In this paper, a vectorized model has been introduced to provide an accurate estimation of the mapping solution with a minimum time overhead. This model is based on a theoretical analysis of the distance matrix and average distance in interconnection networks. Simplifying the search space of possible solutions by a novel matrix-to-vector transformation technique made the proposed model more appropriate and applicable to large-scale applications. The final mapping configuration is computed by comparing vectors to obtain linear time-complexity and make a scalable approach for all sizes of input applications. Moreover, the output of the proposed model can be given to the evolutionary algorithms as the initial solution to save several optimization iterations. We performed extensive experiments to evaluate the execution time overhead and quality of solutions for solving mapping problem. Results show that the proposed vectorized model could save the searching time of evolutionary algorithms up to 70%.
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Data sharing not applicable to this study as no datasets were generated or analyzed during the current study (This article was a theory-based study).
References
Abdel-Basset M, Manogaran G, Rashad H, Zaied AN (2018) A comprehensive review of quadratic assignment problem: variants, hybrids and applications. J Ambient Intell Humaniz Comput 20:1–24
Bhavani K, Jena S (2018) Exchanged folded crossed cube: a new interconnection network for parallel computation. Inf Process Lett 137:40–46
Bibilo PN (2013) The use of models of incompletely specified Boolean functions in logical circuit synthesis based on VHDL descriptions. Autom Control Comput Sci 47(3):122–131
Cela E (2013) The quadratic assignment problem: theory and algorithms. Springer Science & Business Media, Boston
Cheng S, Zhong W, Isaacs KE, Mueller K (2018) Visualizing the topology and data traffic of multi-dimensional torus interconnect networks. IEEE Access 6:57191–57204
Chmaj G, Selvaraj H (2017) Interconnection Networks Efficiency in System-on-Chip Distributed Computing System: Concentrated Mesh and Fat Tree. In: 2017 International Conference on Systems Engineering (ICSEng), pp 277–286
Collier R, Fobel C, Richards L, Grewal G (2012) A formal and empirical analysis of recombination for genetic algorithm-based approaches to the FPGA placement problem. In: 2012 Canadian Conference on Electrical and Computer Engineering (CCECE), pp 1–6
Daryanavard H, Eshghi M, Jahanian A (2015) A fast placement algorithm for embedded just-in-time reconfigurable extensible processing platform. J Supercomput 71(1):121–143
Edwards CS (1980) A branch and bound algorithm for the Koopmans-Beckmann quadratic assignment problem. Combinatorial Optimization II 1980:35–52
Fang J, Yu T, Wei Z (2020) Improved ant colony algorithm based on task scale in network on chip (NoC) mapping. Electronics 9(1):6
Gaffour K, Benhaoua MK, Dey S, Singh AK (2020) Dynamic clustering approach for run-time applications mapping on NoC-based multi/many-core systems. In: 2020 International Conference on Embedded & Distributed Systems (EDiS), pp 15–20
Galea F, Carpov S, Zaourar L (2018) Multi-start simulated annealing for partially-reconfigurable FPGA floorplanning. In: 2018 International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 1335–1338
Jain A, Dwivedi R, Kumar A, Sharma S (2017) Scalable design and synthesis of 3D mesh network on chip. In: Proceeding of International Conference on Intelligent Communication, Control and Devices, pp 661–666
Khan GN, Gharan MO (2019) Application Specific Reconfigurable SoC Interconnection Network Architecture. In: International Conference on Architecture of Computing Systems, pp 322–333
Khan S, Anjum S, Gulzari UA, Afzal MK, Umer T, Ishmanov F (2018) An efficient algorithm for mapping real time embedded applications on NoC architecture. IEEE Access 6:16324–16335
Khan S, Anjum S, Gulzari UA, Umer T, Kim BS (2017) Bandwidth-constrained multi-objective segmented brute-force algorithm for efficient mapping of embedded applications on NoC architecture. IEEE Access 6:11242–11254
Koopmans TC, Beckmann M (1957) Assignment problems and the location of economic activities. Econometrica: journal of the Econometric Society 1:53–76
Li Y, Yan Y, Li W, Liu M (2017) The research of interconnection network on coarse-grained reconfigurable Cipher Logic Array. In: 2017 Advanced Information Technology, Electronic and Automation Control Conference (IAEAC), pp. 1046–1051
Liu J, Huang X, Jiang D, Luo Y (2020) An Energy-aware Spiking Neural Network Hardware Mapping based on Particle Swarm Optimization and Genetic Algorithm. In: 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS), pp. 11–13
Loiola EM, de Abreu NM, Boaventura-Netto PO, Hahn P, Querido T (2007) A survey for the quadratic assignment problem. Eur J Oper Res 176(2):657–690
Maqsood T, Ali S, Malik SU, Madani SA (2015) Dynamic task mapping for network-on-chip based systems. J Syst Architect 61(7):293–306
McKendall A, Li C (2017) A tabu search heuristic for a generalized quadratic assignment problem. J Ind Prod Eng 34(3):221–231
Mohtavipour SM, Shahhoseini HS (2020) A large-scale application mapping in reconfigurable hardware using deep graph convolutional network. In: 2020 International Conference on Computer and Knowledge Engineering (ICCKE), pp 382–387
Mohtavipour SM, Shahhoseini HS (2020b) A link-elimination partitioning approach for application graph mapping in reconfigurable computing systems. J Supercomput 76(1):726–754
Mohtavipour SM, Shahhoseini HS (2020) A low-cost distributed mapping for large-scale applications of reconfigurable computing systems. In: 2020 International Computer Conference, Computer Society of Iran (CSICC), pp 1–6
Nalci Y, Kullu P, Tosun S, Ozturk O (2021) ILP formulation and heuristic method for energy-aware application mapping on 3D-NoCs. J Supercomput 77(3):2667–2680
Punhani A, Kumar P, Nitin N (2017) Three-dimensional topology based on modified diagonal mesh interconnection network. J Telecommun Electron Comput Eng 9(3–6):1–6
Sahni S, Gonzalez T (1976) P-complete approximation problems. J ACM 23(3):555–565
Sahu PK, Manna K, Shah N, Chattopadhyay S (2014) Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip. J Syst Architect 60(7):562–578
Steiger C, Walder H, Platzner M (2004) Operating systems for reconfigurable embedded platforms: Online scheduling of real-time tasks. IEEE Trans Comput 53(11):1393–1407
Tozaki M, Li Y (2017) Topological properties and routing algorithm for the static k-ary n-tree interconnection network. In: 2017 International Symposium on Computing and Networking (CANDAR), pp 318–322
Trobec R, Vasiljević R, Tomašević M, Milutinović V, Beivide R, Valero M (2016) Interconnection networks in petascale computer systems: a survey. ACM Comput Surv 49(3):1–24
Xia Y (2008) Gilmore-Lawler bound of quadratic assignment problem. Front Math China 3(1):109–118
Zhang P, Gao Y, Fierson J, Deng Y (2014) Eigenanalysis-based task mapping on parallel computers with cellular networks. Math Comput 1:1727–1756
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Mohtavipour, S.M., Shahhoseini, H.S. An analytically derived vectorized model for application graph mapping in interconnection networks. J Ambient Intell Human Comput 14, 8899–8911 (2023). https://doi.org/10.1007/s12652-021-03637-4
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DOI: https://doi.org/10.1007/s12652-021-03637-4