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An efficient design of CMOS comparator and folded cascode op-amp circuits using particle swarm optimization with an aging leader and challengers algorithm

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Abstract

Due to the compl ex growth in very large scale integration circuits, the task of optimal analog integrated circuit design by hand is very difficult. Optimization is a time consuming process having many conflicting criteria and a wide range of design parameters. Characterization of complex tradeoffs between nonlinear objectives while assuring required specifications makes analog circuit design a tedious process. The design and optimization processes have to be automated with high accuracy. Evolutionary technique may be a proficient implement for automatic design of analog integrated circuits that has been one of the most challenging topics in VLSI design process. This paper presents a competent approach for optimal designs of two analog circuits, namely, complementary metal oxide semiconductor two-stage comparator with P-type metal oxide semiconductor input driver and n-channel input, folded-cascode operational amplifier. The evolutionary technique used is particle swarm optimization (PSO) with an aging leader and challenger (ALC-PSO). The main aim is to optimize the MOS transistors’ sizes using ALC-PSO in order to reduce the areas occupied by the circuits and to get better performance parameters of the circuits. To exhibit the performance parameters of the circuits, simulation program with integrated circuit emphasis simulation has been carried out by using the optimal values of MOS transistor sizes and other design parameters. Simulation results demonstrate that design specifications are closely met and required functionalities are accommodated. The simulation results also show that the ALC-PSO is superior to the other algorithms in terms of MOS area, and performance parameters like gain, power dissipation, etc. for the examples considered.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, NIT, Durgapur, India

    Bishnu Prasad De, R. Kar & D. Mandal

  2. Department of Electrical Engineering, NIT, Durgapur, India

    S. P. Ghoshal

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  1. Bishnu Prasad De
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  2. R. Kar
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  4. S. P. Ghoshal
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Correspondence to R. Kar.

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De, B.P., Kar, R., Mandal, D. et al. An efficient design of CMOS comparator and folded cascode op-amp circuits using particle swarm optimization with an aging leader and challengers algorithm. Int. J. Mach. Learn. & Cyber. 7, 325–344 (2016). https://doi.org/10.1007/s13042-015-0412-z

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