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High performance fir filter based on vedic mathematics

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Abstract

The FIR digital filter has linear phase, reduced finite precision errors, stability, and productive execution and it is used in Digital Signal Processing (DSP). Signal data processing applications require both signed and unsigned multiplications. Despite its high cost, signed Multiplications are used in a wide number of DSP applications. This paper propose signed vedic multiplier having High speed and low power for finite impulse response. High performance and low power is achieved by parallel operations and adopting Urdhva Triyakbhyam sutra (vertically and crosswise multiplication) in vedic multiplier. The proposed vedic multiplier architecture is implemented and compared with existing conventional radix-4 Booth multiplier.it is observed from the result that the proposed technique results in a 15% increase in speed and 52% reduction in power consumption.

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Abbreviations

DSP:

Digital signal processing

FIR:

Finite impulse response

BW2:

Radix-2 Baugh-Wooley

BR4:

Radix-4 booth-recoded

AWTM:

Appropriate Wallace tree multiplier

CSA:

Carry save adder

FPGA:

Field programmable gate array

RCA:

Ripple carry adder

MRPM:

Modified Russian peasant multiplier

MAC:

Multiplication and accumulation

KNN:

K-nearest neighbor

CAD:

Computer aided design

FRFT:

Fractional Fourier transform

RTL:

Register transfer level

CLA:

Carry look-ahead adder

UT:

Urdhva-Tiryagbyham

LSB:

Least significant bit

MSB:

Most significant bit

EDA:

Electronic design automation

GDS-II:

Graphic data system II

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Correspondence to N. Mohana Priya.

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Priya, N.M., Thangammal, C.B., Seshasayanan, R. et al. High performance fir filter based on vedic mathematics. Int J Syst Assur Eng Manag 14, 829–835 (2023). https://doi.org/10.1007/s13198-023-01899-z

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